參數(shù)資料
型號(hào): ISP1181BBS
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Full-speed Universal Serial Bus peripheral controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC48
封裝: 7 X 7 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-619-2, HVQFN-48
文件頁數(shù): 33/70頁
文件大?。?/td> 341K
代理商: ISP1181BBS
Philips Semiconductors
ISP1181B
Full-speed USB peripheral controller
Product data
Rev. 02 — 07 December 2004
33 of 70
9397 750 13958
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Remark:
There is no protection against writing or reading past a buffer’s boundary,
against writing into an OUT buffer or reading from an IN buffer. Any of these actions
could cause an incorrect operation. Data residing in an OUT buffer are only
meaningful after a successful transaction. Exception: during DMA access of a
double-buffered endpoint, the buffer pointer automatically points to the secondary
buffer after reaching the end of the primary buffer.
12.2.2
Read Endpoint Status
This command is used to read the status of an endpoint FIFO. The command
accesses the Endpoint Status Register, the bit allocation of which is shown in
Table 31
. Reading the Endpoint Status Register will clear the interrupt bit set for the
corresponding endpoint in the Interrupt Register (see
Table 48
).
All bits of the Endpoint Status Register are read-only. Bit EPSTAL is controlled by the
Stall/Unstall commands and by the reception of a SETUP token (see
Section 12.2.3
).
Code (Hex): 50 to 5F —
read (control OUT, control IN, endpoint 1 to 14)
Table 28:
Byte #
(8-bit bus)
0
1
2
3
(N
+
1)
Endpoint FIFO organization
Word #
(16-bit bus)
0 (lower byte)
0 (upper byte)
1 (lower byte)
1 (upper byte)
M = (N + 1) DIV 2
Description
packet length (lower byte)
packet length (upper byte)
data byte 1
data byte 2
data byte N
Table 29:
A0
1
0
0
0
0
0
0
Example of endpoint FIFO access (8-bit bus width)
Phase
Bus lines
command
D[7:0]
data
D[7:0]
data
D[7:0]
data
D[7:0]
data
D[7:0]
data
D[7:0]
data
D[7:0]
Byte #
-
0
1
2
3
4
5
Description
command code (00H to 1FH)
packet length (lower byte)
packet length (upper byte)
data byte 1
data byte 2
data byte 3
data byte 4
Table 30:
A0
1
Example of endpoint FIFO access (16-bit bus width)
Phase
Bus lines
command
D[7:0]
D[15:8]
data
D[15:0]
data
D[15:0]
data
D[15:0]
Word #
-
-
0
1
2
Description
command code (00H to 1FH)
ignored
packet length
data word 1 (data byte 2, data byte 1)
data word 2 (data byte 4, data byte 3)
0
0
0
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