參數(shù)資料
型號(hào): ISP1181BBS
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Full-speed Universal Serial Bus peripheral controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC48
封裝: 7 X 7 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-619-2, HVQFN-48
文件頁(yè)數(shù): 15/70頁(yè)
文件大?。?/td> 341K
代理商: ISP1181BBS
Philips Semiconductors
ISP1181B
Full-speed USB peripheral controller
Product data
Rev. 02 — 07 December 2004
15 of 70
9397 750 13958
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
10. DMA transfer
Direct Memory Access (DMA) is a method to transfer data from one location to
another in a computer system, without intervention of the central processor (CPU).
Many different implementations of DMA exist. The ISP1181B supports two methods:
8237 compatible mode
: based on the DMA subsystem of the IBM personal
computers (PC, AT and all its successors and clones); this architecture uses the
Intel 8237 DMA controller and has separate address spaces for memory and I/O
DACK-only mode
: based on the DMA implementation in some embedded RISC
processors, which has a single address space for both memory and I/O.
The ISP1181B supports DMA transfer for all 14 configurable endpoints (see
Table 4
).
Only one endpoint at a time can be selected for DMA transfer. The DMA operation of
the ISP1181B can be interleaved with normal I/O mode access to other endpoints.
The following features are supported:
Single-cycle or burst transfers (up to 16 bytes per cycle)
Programmable transfer direction (read or write)
Multiple End-Of-Transfer (EOT) sources: external pin, internal conditions,
short/empty packet
Programmable signal levels on pins DREQ, DACK and EOT.
10.1 Selecting an endpoint for DMA transfer
The target endpoint for DMA access is selected via bits EPDIX[3:0] in the DMA
Configuration Register, as shown in
Table 7
. The transfer direction (read or write) is
automatically set by bit EPDIR in the associated ECR, to match the selected endpoint
type (OUT endpoint: read; IN endpoint: write).
Asserting input DACK automatically selects the endpoint specified in the DMA
Configuration Register, regardless of the current endpoint used for I/O mode access.
Table 7:
Endpoint selection for DMA transfer
Endpoint
identifier
EPIDX[3:0]
Transfer direction
EPDIR = 0
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
EPDIR = 1
IN: write
IN: write
IN: write
IN: write
IN: write
IN: write
IN: write
IN: write
IN: write
IN: write
IN: write
1
2
3
4
5
6
7
8
9
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
10
11
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