參數(shù)資料
型號: ISP1181ADGG
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Full-speed Universal Serial Bus peripheral controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PDSO48
封裝: 6.10 MM, PLASTIC, MO-153, SOT-362-1, TSSOP-48
文件頁數(shù): 49/70頁
文件大小: 341K
代理商: ISP1181ADGG
Philips Semiconductors
ISP1181A
Full-speed USB peripheral controller
Product data
Rev. 05 — 08 December 2004
49 of 70
9397 750 13959
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
20. Dynamic characteristics
[1]
Dependent on the crystal oscillator start-up time.
[1]
[2]
[3]
Test circuit: see
Figure 33
.
Excluding the first transition from Idle state.
Characterized only, not tested. Limits guaranteed by design.
Table 55:
V
CC
= 3.3 V
±
10 % or 5.0 V
±
10 %; V
GND
= 0 V; T
amb
=
40
°
C to
+
85
°
C; unless otherwise specified.
Symbol
Parameter
Conditions
Reset
t
W(RESET)
pulse width on input RESET
crystal oscillator running
crystal oscillator stopped
Crystal oscillator
f
XTAL
crystal frequency
Dynamic characteristics
Min
Typ
Max
Unit
50
-
-
3
[1]
-
-
μ
s
ms
-
6
-
MHz
Table 56:
V
CC
= 3.3 V
±
10 % or 5.0 V
±
10 %; V
GND
= 0 V; T
amb
=
40
°
C to
+
85
°
C; C
L
= 50 pF; R
PU
= 1.5 k
on D
+
to V
TERM
; unless
otherwise specified.
Symbol
Parameter
Conditions
Driver characteristics
t
FR
rise time
C
L
= 50 pF;
10 % to 90 % of
|
V
OH
V
OL
|
t
FF
fall time
C
L
= 50 pF;
90 % to 10 % of
|
V
OH
V
OL
|
FRFM
differential rise/fall time
matching (t
FR
/t
FF
)
V
CRS
output signal crossover
voltage
Data source timing
t
FEOPT
source EOP width
see
Figure 15
t
FDEOP
source differential
data-to-EOP transition
skew
Receiver timing
t
JR1
receiver data jitter
tolerance for consecutive
transitions
t
JR2
receiver data jitter
tolerance for paired
transitions
t
FEOPR
receiver SE0 width
accepted as EOP; see
Figure 15
t
FST
width of SE0 during
differential transition
Figure 17
Dynamic characteristics: analog I/O pins (D
+
, D
)
[1]
Min
Typ
Max
Unit
4
-
20
ns
4
-
20
ns
[2]
90
-
111.11
%
[2][3]
1.3
-
2.0
V
[3]
160
-
-
175
+
5
ns
ns
see
Figure 15
[3]
2
see
Figure 16
[3]
18.5
-
+
18.5
ns
see
Figure 16
[3]
9
-
+
9
ns
[3]
82
-
-
ns
rejected as EOP; see
[3]
-
-
14
ns
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