參數(shù)資料
型號(hào): ISP1181ADGG
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Full-speed Universal Serial Bus peripheral controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PDSO48
封裝: 6.10 MM, PLASTIC, MO-153, SOT-362-1, TSSOP-48
文件頁(yè)數(shù): 27/70頁(yè)
文件大?。?/td> 341K
代理商: ISP1181ADGG
Philips Semiconductors
ISP1181A
Full-speed USB peripheral controller
Product data
Rev. 05 — 08 December 2004
27 of 70
9397 750 13959
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
12.1.3
Write/Read Mode Register
This command is used to access the ISP1181A Mode Register, which consists of
1 byte (bit allocation: see
Table 18
). In 16-bit bus mode the upper byte is ignored.
The Mode Register controls the DMA bus width, resume and suspend modes,
interrupt activity and SoftConnect operation. It can be used to enable debug mode,
where all errors and Not Acknowledge (NAK) conditions will generate an interrupt.
Code (Hex): B8/B9 —
write/read Mode Register
Transaction —
write/read 1 byte
[1]
Unchanged by a bus reset.
Table 17:
Bit
7
6 to 0
Address Register: bit description
Symbol
Description
DEVEN
A logic 1 enables the device.
DEVADR[6:0]
This field specifies the USB device address.
Table 18:
Bit
Symbol
Reset
Access
Mode Register: bit allocation
7
DMAWD
0
[1]
R/W
6
5
4
3
2
1
0
reserved
0
R/W
GOSUSP
0
R/W
reserved
0
R/W
INTENA
0
[1]
R/W
DBGMOD
0
[1]
R/W
reserved
0
[1]
R/W
SOFTCT
0
[1]
R/W
Table 19:
Bit
7
Mode Register: bit description
Symbol
DMAWD
Description
A logic 1 selects 16-bit DMA bus width (bus configuration modes
0 and 2). A logic 0 selects 8-bit DMA bus width. Bus reset value:
unchanged.
reserved
Writing a logic 1 followed by a logic 0 will activate ‘suspend’
mode.
reserved
A logic 1 enables all interrupts. Bus reset value: unchanged.
A logic 1 enables debug mode. where all NAKs and errors will
generate an interrupt. A logic 0 selects normal operation, where
interrupts are generated on every ACK (bulk endpoints) or after
every data transfer (isochronous endpoints). Bus reset value:
unchanged.
reserved
A logic 1 enables SoftConnect (see
Section 7.4
). This bit is
ignored if EXTPUL = 1 in the Hardware Configuration Register
(see
Table 20
). Bus reset value: unchanged.
6
5
-
GOSUSP
4
3
2
-
INTENA
DBGMOD
1
0
-
SOFTCT
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