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參數(shù)資料
| 型號： | ISP1181ABS |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | INDUCTOR 1.0NH +-.3NH FIXED SMD |
| 中文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQCC48 |
| 封裝： | 7 X 7 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-619-2, HVQFN-48 |
| 文件頁數(shù)： | 29/70頁 |
| 文件大小： | 341K |
| 代理商： | ISP1181ABS |
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Philips Semiconductors
ISP1181A
Full-speed USB peripheral controller
Product data
Rev. 05 — 08 December 2004
29 of 70
9397 750 13959
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
12.1.5
Write/Read Interrupt Enable Register
This command is used to individually enable/disable interrupts from all endpoints, as
well as interrupts caused by events on the USB bus (SOF, SOF lost, EOT, suspend,
resume, reset). A bus reset will not change any of the programmed bit values.
The command accesses the Interrupt Enable Register, which consists of 4 bytes. The
bit allocation is given in
Table 22
.
Code (Hex): C2/C3 —
write/read Interrupt Enable Register
Transaction —
write/read 4 bytes
6
DRQPOL
Selects DREQ signal polarity (0 = active LOW, 1 = active
HIGH). Bus reset value: unchanged.
Selects DACK signal polarity (0 = active LOW, 1 = active HIGH).
Bus reset value: unchanged.
Selects EOT signal polarity (0 = active LOW, 1 = active HIGH).
Bus reset value: unchanged.
A logic 1 enables remote wake-up via a LOW level on input CS
(For wake-up on CS to work, V
BUS
must be present.).
Bus reset value: unchanged.
A logic 1 enables powering-off during ‘suspend’ state. Output
SUSPEND is configured as a power switch control signal for
external devices (HIGH during ‘suspend’). This value should
always be initialized to logic 1. Bus reset value: unchanged.
Selects the interrupt signalling mode on output INT (0 = level,
1 = pulsed). In pulsed mode an interrupt produces an 166 ns
pulse. See
Section 13
for details. Bus reset value: unchanged.
Selects INT signal polarity (0 = active LOW, 1 = active HIGH).
Bus reset value: unchanged.
5
DAKPOL
4
EOTPOL
3
WKUPCS
2
PWROFF
1
INTLVL
0
INTPOL
Table 21:
Bit
Hardware Configuration Register: bit description
…continued
Symbol
Description
Table 22:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Interrupt Enable Register: bit allocation
31
30
29
28
27
26
25
24
reserved
0
0
0
0
0
0
0
0
R/W
23
IEP14
0
R/W
15
IEP6
0
R/W
R/W
22
IEP13
0
R/W
14
IEP5
0
R/W
R/W
21
IEP12
0
R/W
13
IEP4
0
R/W
R/W
20
IEP11
0
R/W
12
IEP3
0
R/W
R/W
19
IEP10
0
R/W
11
IEP2
0
R/W
R/W
18
IEP9
0
R/W
10
IEP1
0
R/W
R/W
17
IEP8
0
R/W
9
IEP0IN
0
R/W
R/W
16
IEP7
0
R/W
8
IEP0OUT
0
R/W
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISP1181ABS,518 | 功能描述:USB 接口集成電路 USB 1.1 ADV DEVICE RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1181ABS,551 | 功能描述:USB 接口集成電路 USB 1.1 ADVANCED DEVICE RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1181ABS,557 | 功能描述:USB 接口集成電路 DO NOT USE ORDER -S OR -T PART RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1181ABSGE | 功能描述:IC USB CNTRLR FULL-SPD 48-HVQFN RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應商設備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| ISP1181ABS-S | 功能描述:IC USB HOST CTRL FULL-SPD 48HVQF RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應商設備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
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