參數(shù)資料
型號(hào): ISP1181ABS
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: INDUCTOR 1.0NH +-.3NH FIXED SMD
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC48
封裝: 7 X 7 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-619-2, HVQFN-48
文件頁數(shù): 25/70頁
文件大?。?/td> 341K
代理商: ISP1181ABS
Philips Semiconductors
ISP1181A
Full-speed USB peripheral controller
Product data
Rev. 05 — 08 December 2004
25 of 70
9397 750 13959
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
[1]
[2]
[3]
[4]
[5]
[6]
[7]
With N representing the number of bytes, the number of words for 16-bit bus width is: (N + 1) DIV 2.
When accessing an 8-bit register in 16-bit mode, the upper byte is invalid.
In 8-bit bus mode this command requires more time to complete than other commands. See
Table 58
.
During isochronous transfer in 16-bit mode, because N
1023, the firmware must take care of the upper byte.
Validating an OUT endpoint buffer causes unpredictable behavior of ISP1181A.
Clearing an IN endpoint buffer causes unpredictable behavior of ISP1181A.
Reads a copy of the Status Register: executing this command does not clear any status bits or interrupt bits.
12.1 Initialization commands
Initialization commands are used during the enumeration process of the USB
network. These commands are used to configure and enable the embedded
endpoints. They also serve to set the USB assigned address of ISP1181A and to
perform a device reset.
12.1.1
Write/Read Endpoint Configuration
This command is used to access the Endpoint Configuration Register (ECR) of the
target endpoint. It defines the endpoint type (isochronous or bulk/interrupt), direction
(OUT/IN), FIFO size and buffering scheme. It also enables the endpoint FIFO. The
register bit allocation is shown in
Table 14
. A bus reset will disable all endpoints.
The allocation of FIFO memory only takes place after
all
16 endpoints have been
configured in sequence (from endpoint 0 OUT to endpoint 14). Although the control
endpoints have fixed configurations, they must be included in the initialization
sequence and be configured with their default values (see
Table 4
). Automatic FIFO
allocation starts when endpoint 14 has been configured.
Unstall Endpoint n
(n = 1 to 14)
Check Control OUT Status
[7]
Endpoint 1 to 14
82 to 8F
-
Endpoint Status Image Register
endpoint 0 OUT
Endpoint Status Image Register
endpoint 0 IN
Endpoint Status Image Register n
endpoint 1 to 14
Endpoint 0 IN and OUT
D0
read 1 byte
[2]
Check Control IN Status
[7]
D1
read 1 byte
[2]
Check Endpoint n Status
(n = 1 to 14)
[7]
Acknowledge Setup
General commands
Read Control OUT Error Code
D2 to DF
read 1 byte
[2]
F4
-
[3]
Error Code Register
endpoint 0 OUT
Error Code Register
endpoint 0 IN
Error Code Register
endpoint 1 to 14
all registers with write access
Scratch Register
Frame Number Register
Chip ID Register
Interrupt Register
A0
read 1 byte
[2]
Read Control IN Error Code
A1
read 1 byte
[2]
Read Endpoint n Error Code
(n = 1 to 14)
Unlock Device
Write/Read Scratch Register
Read Frame Number
Read Chip ID
Read Interrupt Register
A2 to AF
read 1 byte
[2]
B0
B2/B3
B4
B5
C0
write 2 bytes
write/read 2 bytes
read 1 or 2 bytes
read 2 bytes
read 4 bytes
Table 13:
Name
Command and register summary
…continued
Destination
Code (Hex)
Transaction
[1]
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