參數(shù)資料
型號: ISP1181ABS
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: INDUCTOR 1.0NH +-.3NH FIXED SMD
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC48
封裝: 7 X 7 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-619-2, HVQFN-48
文件頁數(shù): 16/70頁
文件大小: 341K
代理商: ISP1181ABS
Philips Semiconductors
ISP1181A
Full-speed USB peripheral controller
Product data
Rev. 05 — 08 December 2004
16 of 70
9397 750 13959
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
10.2 8237 compatible mode
The 8237 compatible DMA mode is selected by clearing bit DAKOLY in the Hardware
Configuration Register (see
Table 20
). The pin functions for this mode are shown in
Table 8
.
The DMA subsystem of an IBM compatible PC is based on the Intel 8237 DMA
controller. It operates as a ‘fly-by’ DMA controller: the data is not stored in the DMA
controller, but it is transferred between an I/O port and a memory address. A typical
example of ISP1181A in 8237 compatible DMA mode is given in
Figure 4
.
The 8237 has two control signals for each DMA channel: DREQ (DMA Request) and
DACK (DMA Acknowledge). General control signals are HRQ (Hold Request) and
HLDA (Hold Acknowledge). The bus operation is controlled via MEMR (Memory
Read), MEMW (Memory Write), IOR (I/O read) and IOW (I/O write).
12
13
14
1101
1110
1111
OUT: read
OUT: read
OUT: read
IN: write
IN: write
IN: write
Table 7:
Endpoint selection for DMA transfer
…continued
Endpoint
identifier
EPIDX[3:0]
Transfer direction
EPDIR = 0
EPDIR = 1
Table 8:
Symbol
DREQ
DACK
EOT
RD
WR
8237 compatible mode: pin functions
Description
DMA request
DMA acknowledge
end of transfer
read strobe
write strobe
I/O
O
I
I
I
I
Function
ISP1181A requests a DMA transfer
DMA controller confirms the transfer
DMA controller terminates the transfer
instructs ISP1181A to put data on the bus
instructs ISP1181A to get data from the
bus
Fig 4.
ISP1181A in 8237 compatible DMA mode.
AD0,
DATA1 to DATA15
CPU
004aaa022
RAM
ISP1181A
DMA
CONTROLLER
8237
DREQ
DREQ
DACK
HRQ
HLDA
HRQ
HLDA
DACK
IOR
IOW
MEMR
MEMW
RD
WR
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