參數(shù)資料
型號(hào)： ISL6271ACR-T
廠商： INTERSIL CORP
元件分類(lèi)： 穩(wěn)壓器
英文描述： Integrated XScale Regulator
中文描述： 0.8 A SWITCHING REGULATOR, PQCC20
封裝： 4 X 4 MM, LEAD FREE, PLASTIC, MO-220-VGGD, QFN-20
文件頁(yè)數(shù)： 11/16頁(yè)
文件大?。?/td> 588K
代理商： ISL6271ACR-T
11
FN9171.1
VID and Slew Rate Program Register
In a typical XScale configuration, the processor’s “Power
Manager” will issue the voltage and slew rate commands to
the ISL6271A over its PWR_ I
2
C bus after the ISL6271A
acknowledges its address. The data byte is composed of two
pieces of ‘set’ information: The prescribed voltage level
embedded in bits D0-D3, and the prescribed transition slew
rate (from the previous voltage to the target voltage)
embedded in bits D4-D5. Each set of bits is transmitted MSB
first. This protocol is depicted in Figure 18.
Application Guidelines
Every effort should be made to place the ISL6271A as close
as possible to the processor, with the orientation favoring the
shortest voltage routing. The regulator input capacitors
should be located close to their respective input pins.
All output capacitors should be kept close to their respective
output pins with the ground pins connected immediately to
the ground plane. Care should be taken to avoid routing
sensitive, high impedance signals near the PHASE pin on
the controller, and the attendant PCB traces.
To minimize switching noise, it is important to keep the loop
area associated with the phase node and output filter as
short as possible. It is also important that the input voltage
decoupling capacitor C7 be located as close to the PVCC
pin as possible and that it has a low impedance return path
to the PGND pin. In general a good approach to layout is to
consider how switching current flows in a circuit, and to
minimize the loop area associated with this current. In the
case of the switching regulator, current flows from C7
through the internal upper P-MOSFET, to the load through
the output filter and back to the PGND pin.
To maximize the
effectiveness of any decoupling capacitor, minimize the
parasitic inductance between the capacitor and the circuit it
is decoupling.
Notice that Figure 19 illustrates the SIGNAL
ground with RED highlighting. All components associated
with these terminals should be tied together first. Be sure to
make only one connection between this net and the PGND
pin to avoid ground loops and noise injection points into
sensitive analog circuitry.
FIGURE 18. INTERFACE BIT DEFINITION AND PROTOCOL
S
0
0 0
1
A3 A2 A1 A0
1 0
0
0 0
W
S
0
A6 A5 A4 A3 A2 A1 A0 W A
0 0
1
1 0
0
1
SLAVE ADDRESS
COMMAND BYTE
START
P
0
ASTOP
D0
D1
D2
D3
D4
D5
X
VOLTAGE
SET
SLEW
X
I
2
C SEND BYTE PROTOCOL
I
2
C RECEIVE BYTE PROTCOL
DATA BYTE
SLAVE ADDRESS
START
0
A
A6 A5
A4
D0
D6
D7
A STOP
1
P
D1
D2
D3
D4
D5
FIGURE 19. TYPICAL APPLICATION CIRCUIT
L1
4.7μH
Rcomp, 50K
C5
2.2μF
X5R
C8
2.2μF
X5R
EN
BFLT#
SDA/VID1
SCL/VID0
VSRAM
VPLL
FB
VOUT
PHASE
PVCC
LVCC
C4
10nF
X7R
SOFT
GND
C2
5k
BBAT
≤
VCC
COIN CELL
BACK-UP
PGOOD
BBAT
PGND
VID2
VID3
VCC
VIDEN
Single point connection
between PGND and GND pins
Power ground. Minimize the loop area associated
with L1, C6 and the PHASE and PGND pins.
REG. EN
FAULT
PWR_I2C
VCC_SRAM
VCC_PLL
VCC_CORE
C3
Li-ion
4.2V
TO
2.60V
R7, 10
C7
10μF
XScale μP
{
ISL6271A
1.8V
OR 2.5V
C6
10μF
X5R
5k
5k
0.1μF
2.2μF
ISL6271A
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