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參數資料
| 型號： | ISL5216KI |
| 廠商： | INTERSIL CORP |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | Four-Channel Programmable Digital DownConverter |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA196 |
| 封裝： | 12 X 12 MM, 0.80 MM PITCH, PLASTIC, BGA-196 |
| 文件頁數： | 21/65頁 |
| 文件大?。?/td> | 1384K |
| 代理商： | ISL5216KI |
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21
63
Reserved
Set to 0.
66:64
Coefficient Memory
Block Size
66:64
Memory Block Size
0
8
1
16
2
32
3
64
4
128
5
256
6
512
7
(Modulo addressing can be used, but is usually not needed. If not needed this bit field can always be
set to 7).
1024
75:67
Number of FIR
Outputs
Number of FIR outputs (range is 1 to 512, load w/ desired value minus 1).
This is usually equal to the total decimation that follows the filter.
84:76
Read Address
Pointer Step
Read address pointer step (for next run). This is usually equal to the filter decimation times the number
of outputs from the instruction.
93:85
Initial Address Offset
Initial address offset (to ADDRB). This is the offset from the start address to other end of filter.
For symmetric filters, usually equal to -1 x (number of taps -1).
95:94
Reserved
Set to 0
104:96
Memory Reads Per
FIR Output
This is based on the number of taps (load with value below minus 1).
Type
Value
Symmetric, even number of taps
(taps/2) or
fl
oor((taps+1)/2).
Symmetric, odd number of taps
(taps+1)/2 or
fl
oor((taps+1)/2).
Decimating HBF
(taps+5)/4.
Asymmetric
taps.
Complex
taps .
Resampling
taps/phase (six taps per phase for the ROM’d coef
fi
cients provided).
Interpolating HBF
(taps+5)/4-1 .
106:105
Clocks Per
Memory Read
Set to 0 for all but complex FIR, which is set to 1.
115:107
Data Memory
Step Size 1
(ADDRA) Step size for all but the last tap computation of the FIR.
Set to -2 for HBF, -1 otherwise.
117:116
Data Memory
Step Size 2
(ADDRA) Step size for last tap computation. Set to -1.
117:116
Step size
0
0
1
-1
2
-2
3
step size value.
119:118
Data Memory
Address Offset Step
(ADDRB) Step size for opposite end of symmetric filter. Set to +2 for Decimating HBF, to +1 for others
(the B data is not used for asymmetric, resampling, and complex filters).
122:120
Coefficient Memory
Step Size
(ADDRC) Usually set to 1.
122:120
Step size
0
0
1
1
2
2
3
4
4
8
5
16
6
32
7
64
INSTRUCTION BIT FIELDS (Continued)
BIT
POSITIONS
FUNCTION
DESCRIPTION
ISL5216
相關PDF資料 |
PDF描述 |
|---|---|
| ISL5216 | Four-Channel Programmable Digital DownConverter |
| ISL5217EVAL1 | Quad Programmable Up Converter |
| ISL5217KI | Quad Programmable Up Converter |
| ISL5217 | Quad Programmable Up Converter |
| ISL5217KIZ | Quad Programmable Up Converter |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ISL5216KI-1 | 功能描述:上下轉換器 QUAD DIGITAL DOWNCONVERTER,IND TEMP,1.OMM PITCH BGA PACKAG RoHS:否 制造商:Texas Instruments 產品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| ISL5216KI-1Z | 功能描述:上下轉換器 W/ANL QD DIG DWNCNVRTR 1 OM PITCH RoHS:否 制造商:Texas Instruments 產品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| ISL5216KIZ | 功能描述:上下轉換器 W/ANNEAL QD DIGTL DWNCNVRTR IND TEMP RoHS:否 制造商:Texas Instruments 產品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| ISL5217 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Quad Programmable Up Converter |
| ISL5217_05 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Quad Programmable Up Converter |
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