- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄296249 > IS41LV44004-50JI (INTEGRATED SILICON SOLUTION INC) 4M X 4 EDO DRAM, 50 ns, PDSO24 PDF資料下載
參數(shù)資料
| 型號： | IS41LV44004-50JI |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 4M X 4 EDO DRAM, 50 ns, PDSO24 |
| 封裝： | 0.300 INCH, SOJ-24 |
| 文件頁數(shù)： | 17/19頁 |
| 文件大?。?/td> | 157K |
| 代理商： | IS41LV44004-50JI |
Integrated Silicon Solution, Inc. — 1-800-379-4774
7
Rev. D
06/24/01
IS41C4400X
IS41LV4400X SERIES
ISSI
AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-50
-60
Symbol
Parameter
Min.
Max.
Min.
Max.
Units
tRWL
Write Command to
RAS Lead Time(17)
13
—
15
—
ns
tCWL
Write Command to
CAS Lead Time(17, 21)
8
—
10
—
ns
tWCS
Write Command Setup Time(14, 17, 20)
0
—
0
—
ns
tDHR
Data-in Hold Time (referenced to
RAS)39
—
39
—
ns
tACH
Column-Address Setup Time to
CAS
15
—
15
—
ns
Precharge during WRITE Cycle
tOEH
OE Hold Time from WE during
8
—
10
—
ns
READ-MODIFY-WRITE cycle(18)
tDS
Data-In Setup Time(15, 22)
0
—
0
—
ns
tDH
Data-In Hold Time(15, 22)
8
—
10
—
ns
tRWC
READ-MODIFY-WRITE Cycle Time
108
—
133
—
ns
tRWD
RAS to WE Delay Time during
64
—
77
—
ns
READ-MODIFY-WRITE Cycle(14)
tCWD
CAS to WE Delay Time(14, 20)
26
—
32
—
ns
tAWD
Column-Address to
WE Delay Time(14)
39
—
47
—
ns
tPC
EDO Page Mode READ or WRITE
20
—
25
—
ns
Cycle Time
tRASP
RAS Pulse Width in EDO Page Mode
50
100K
60
100K
ns
tCPA
Access Time from
CAS Precharge(15)
—
30
—
35
ns
tPRWC
EDO Page Mode READ-WRITE
56
—
68
—
ns
Cycle Time
tCOH
Data Output Hold after
CAS LOW
5
—
5
—
ns
tOFF
Output Buffer Turn-Off Delay from
0
12
0
15
ns
CAS or RAS(13,15,19, 24)
tWHZ
Output Disable Delay from
WE
310
3
10
ns
tCSR
CAS Setup Time (CBR REFRESH)(20, 25)
5
—
5
—
ns
tCHR
CAS Hold Time (CBR REFRESH)( 21, 25)
8
—
10
—
ns
tORD
OE Setup Time prior to RAS during
0
—
0
—
ns
HIDDEN REFRESH Cycle
tREF
Auto Refresh Period
2,048 Cycles
—
32
—
32
ms
4,096 Cycles
—
64
—
64
tT
Transition Time (Rise or Fall)(2, 3)
150
1
50
ns
AC TEST CONDITIONS
Output load:
Two TTL Loads and 50 pF
Input timing reference levels: VIH = 2.4V, VIL = 0.8V
Output timing reference levels: VOH = 2.0V, VOL = 0.8V
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IS42VS16160D-75BLI | 16M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA54 |
| IS45VS16160D-8BLA2 | 16M X 16 SYNCHRONOUS DRAM, 6 ns, PBGA54 |
| IS43R32800B-5BL | 8M X 32 DDR DRAM, 0.7 ns, PBGA144 |
| IS61C512-25TI | x8 SRAM |
| IS61C512-35J | x8 SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS41LV44004-50T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 EDO Page Mode DRAM |
| IS41LV44004-50TI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 EDO Page Mode DRAM |
| IS41LV44004-60J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 EDO Page Mode DRAM |
| IS41LV44004-60JI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 EDO Page Mode DRAM |
| IS41LV44004-60T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 EDO Page Mode DRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。