參數(shù)資料
型號: IS41LV44004-50JI
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: 4M X 4 EDO DRAM, 50 ns, PDSO24
封裝: 0.300 INCH, SOJ-24
文件頁數(shù): 15/19頁
文件大?。?/td> 157K
代理商: IS41LV44004-50JI
Integrated Silicon Solution, Inc. — 1-800-379-4774
5
Rev. D
06/24/01
IS41C4400X
IS41LV4400X SERIES
ISSI
ELECTRICAL CHARACTERISTICS(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol
Parameter
Test Condition
VCC
Speed
Min.
Max.
Unit
IIL
Input Leakage Current
Any input 0V
≤ VIN ≤ Vcc
–55
A
Other inputs not under test = 0V
IIO
Output Leakage Current
Output is disabled (Hi-Z)
–55
A
0V
≤ VOUT ≤ Vcc
VOH
Output High Voltage Level
IOH = –5.0 mA, Vcc = 5V
2.4
V
IOH = –2.0 mA, Vcc = 3.3V
VOL
Output Low Voltage Level
IOL = 4.2 mA, Vcc = 5V
0.4
V
IOL = 2 mA, Vcc = 3.3V
ICC1
Standby Current: TTL
RAS, CAS
≥ VIH Commercial
5V
2mA
3.3V
0.5
Industrial
5V
3
3.3V
2
ICC2
Standby Current: CMOS
RAS, CAS
≥ VCC – 0.2V
5V
1mA
3.3V
0.5
ICC3
Operating Current:
RAS, CAS,
-50
120
mA
Random Read/Write(2,3,4)
Address Cycling, tRC = tRC (min.)
-60
110
Average Power Supply Current
ICC4
Operating Current:
RAS = VIL, CAS,
-50
90
mA
EDO Page Mode(2,3,4)
Cycling tPC = tPC (min.)
-60
80
Average Power Supply Current
ICC5
Refresh Current:
RAS Cycling, CAS
≥ VIH
-50
120
mA
RAS-Only(2,3)
tRC = tRC (min.)
-60
110
Average Power Supply Current
ICC6
Refresh Current:
RAS, CAS Cycling
-50
120
mA
CBR(2,3,5)
tRC = tRC (min.)
-60
110
Average Power Supply Current
Notes:
1. An initial pause of 200 s is required after power-up followed by eight
RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight
RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
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