參數(shù)資料
型號(hào)： INT5130
廠商： Electronic Theatre Controls, Inc.
英文描述： Integrated Powerline MAC/PHY Transceiver
中文描述： 綜合電力線MAC /物理層收發(fā)器
文件頁數(shù)： 2/38頁
文件大?。?/td> 1352K
代理商： INT5130
INTELLON CONFIDENTIAL
Rev 8.1
2
ADVANCE INFORMATION
INT5130 Integrated Powerline MAC /PHY Transceiver Technical Data Sheet
The INT5130 implements Intellon’s patented PowerPacket OFDM technology and is fully compliant with the
HomePlug Powerline Alliance
Industry Specification v1.0
. Specifically tailored to reliably deliver up to 14
Mbps over the difficult powerline communication environment, the INT5130 combats deep attenuation notches,
noises sources, and multi-path fading by allocating usable frequencies according to the signal to noise ratio
(SNR). Synchronization is achieved in low SNR channels without the use of pilot carriers. The MAC
implements a CSMA/CA scheme with prioritization and automatic repeat request (ARQ) for reliable delivery of
Ethernet packets via packet encapsulation. Built-in quality-of-service (QoS) features provide the necessary
bandwidth for multimedia payloads including voice, data, audio, and video. Prioritized random access along with
segment bursting minimizes the demands on the receiver resources and maximizes the throughput of the
network while still providing excellent latency response and jitter performance. The INT5130’s contention-free
access capability extends this concept of segment bursting to allow the transmission of multiple frames over
the powerline without relinquishing the control of the medium. Utilizing contention-free access, a single station
may act as a controller for the entire network.
System designers have the option of embedding PowerPacket-specific control information within the packet
stream for optimal control and performance or may choose to provide this information via the separate
E
2
PROM interface. Providing this configuration and control information through a separate E
2
PROM interface
allows the system designer to leverage standard Ethernet drivers.
The INT5130 operates on both 2.5V and 3.3V supplies, offers 5V I/O tolerance, and is packaged in a 144-pin
LQFP. Intellon offers a complete solution for powerline communication applications by providing the INT5130 in
conjunction with the INT1000 Analog Conversion IC.
Functional Block Diagram
TX[3:0],TXCLK,TXEN,TX_ER
COL,CRS
- OR -
RXD,RXCLK,RXEN
TXD,TXCLK,TXEN
COL,TXBSY
PHY
Core
PowerPacket MAC
PowerPacket PHY
INT5130
Interface Block
MII/GPSI
Interface
DMA
&
Link
Sequencer
RISC
uProc
Core
ROM
RAM
Arbiter
Buffer
RAM
AFE
Interface
JTAG
Port
LED
Control
CLK OUT
CLK IN
RESET
Config
Regs
MDCLK/MDIO
- OR -
SPI Control
SDI,SDO,SCLK,CS
E
2
PROM
Control
Configuration
EEPROM
Control
JTAG
Control
MII/GPSI
Select
MII
MDI/SPI
Select
MDIO Control
Power
&
GND
ADC
DAC
IFace
Gain
Control
MDIO
Address
Select
LEDs
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