參數(shù)資料
型號: INT5130
廠商: Electronic Theatre Controls, Inc.
英文描述: Integrated Powerline MAC/PHY Transceiver
中文描述: 綜合電力線MAC /物理層收發(fā)器
文件頁數(shù): 16/38頁
文件大?。?/td> 1352K
代理商: INT5130
INTELLON CONFIDENTIAL
Rev 8.1
16
ADVANCE INFORMATION
INT5130 Integrated Powerline MAC /PHY Transceiver Technical Data Sheet
P
P
Case 6
TX only
P
Case 7
TX overrun
Frame
dropped
P
Case 8
Collision
MII_TXEN
MII_CRS
MII_COL
MII_RXDV
MII_RX[3:0]
MII_TX[3:1], MII_TX0
Figure 9: MII Flow Control Overview Part 2
MII Frame Structure
The frame structure transmitted on the MII or GPSI interface is the following sequence of fields:
Interframe Gap
Preamble
Start Frame Delimiter
Data
Interframe Gap
A period on the MII interface during which no data activity occurs on the MII.
Preamble
Begins a frame transmission that consists of 7 octets with the following bit values…
10101010 10101010 10101010 10101010 10101010 10101010 10101010
The preamble is stripped by the INT5130 when transmitting (the preamble is not transmitted on the
PLC medium) and pre-pended by the INT5130 when receiving.
Start Frame Delimiter
Indicates the start of a frame and follows the preamble. The SFD bit sequence is 10101011.
The start frame delimiter is stripped by the INT5130 when transmitting (the SFD is not transmitted
on the PLC medium) and pre-pended by the INT5130 when receiving.
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