參數(shù)資料
型號： IDTSSTE32882HLBBKG
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 36/73頁
文件大?。?/td> 0K
描述： IC REGISTERING CLK DRIVER 176BGA
標(biāo)準(zhǔn)包裝： 208
類型： 時鐘緩沖器/驅(qū)動器，多路復(fù)用器
PLL： 是
主要目的： 存儲器，DDR3，RDIMM
輸入： CMOS
輸出： CMOS
電路數(shù)： 1
比率 - 輸入:輸出： 5:60
差分 - 輸入:輸出： 是/是
頻率 - 最大： 810MHz
電源電壓： 1.282 V ~ 1.575 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 176-TFBGA
供應(yīng)商設(shè)備封裝： 176-CABGA（6x15）
包裝： 托盤
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
41
SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
Two Parity-Error Occurrences Separated by two Clock Cycles of no Error Occurrence
1 CK left out for better visibility.
The next figure shows the parity diagram with two parity-error occurrences; during chip-select and chip-deselect modes. The
diagram assumes the occurrence of both parity errors when data is clocked in at the n and n+1 input clock cycles (PAR_IN
clocked in on the n+1 and n+2 input clock cycles). Parity error in the chip-select mod is detected, but parity error in the
chip-deselect mode is ignored.
Parity-Error Occurrence In Chip-Deselect Mode
1 CK left out for better visibility.
The next figure shows the parity diagram with two parity-error occurrences; during normal operation and during control
register programming. The diagram assumes the occurrence of both parity errors when data is clocked in at the n and n+3 input
clock cycles (PAR_IN clocked in on the n+1 and n+4 input clock cycles). The data on the n+3 input clock pulse is intended for
the control mode register. Parity error during control mode register programming is detected and the parity functionality is the
same as during normal operation. If a parity error occurs, the command is ignored.
CK(1)
CA
Input
PAR_IN
CA0
P0
CA1
P1
CA2
P2
ERROUT
n
n+1
n+2
n+3
n+4
n+5
n+6
ERROUT resulting from CA0 - P0, followed by 2nd error in CA3 - P3
n+7
n+8
n+9
CA3
P3
P4
CA4
CA5
P5
CK(1)
CA
Input
PAR_IN
CA0
P0
CA1
P1
CA2
P2
ERROUT
n
n+1
n+2
n+3
n+4
n+5
n+6
ERROUT resulting from CA0 - P0, subsequent parity errors during DCSx high ignored
DCSx
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參數(shù)描述
IDTSSTE32882HLBBKG8 制造商:Integrated Device Technology Inc 功能描述:IC REGISTERING CLK DRIVER 176BGA
IDTSSTE32882KA1AKG 功能描述:IC REGISTERING CLK DRIVER 176BGA RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT
IDTSSTE32882KA1AKG8 制造商:Integrated Device Technology Inc 功能描述:IC REGISTERING CLK DRIVER 176BGA
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IDTSSTUB32S869AHLF 功能描述:IC REGISTERED BUFFER 150-TFBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 信號緩沖器，中繼器，分配器 系列:- 標(biāo)準(zhǔn)包裝:160 系列:- 類型:轉(zhuǎn)發(fā)器 Tx/Rx類型:以太網(wǎng) 延遲時間:- 電容 - 輸入:- 電源電壓:2.37 V ~ 2.63 V 電流 - 電源:60mA 安裝類型:表面貼裝 封裝/外殼:64-TQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-TQFP-EP（10x10） 包裝:托盤 其它名稱:Q5134101
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