參數(shù)資料
型號(hào): IDTSSTE32882HLBBKG
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 20/73頁(yè)
文件大?。?/td> 0K
描述: IC REGISTERING CLK DRIVER 176BGA
標(biāo)準(zhǔn)包裝: 208
類型: 時(shí)鐘緩沖器/驅(qū)動(dòng)器,多路復(fù)用器
PLL:
主要目的: 存儲(chǔ)器,DDR3,RDIMM
輸入: CMOS
輸出: CMOS
電路數(shù): 1
比率 - 輸入:輸出: 5:60
差分 - 輸入:輸出: 是/是
頻率 - 最大: 810MHz
電源電壓: 1.282 V ~ 1.575 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 176-TFBGA
供應(yīng)商設(shè)備封裝: 176-CABGA(6x15)
包裝: 托盤
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
27
SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
6
Hold (tH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)MAX and the
first crossing of VREF(DC). Hold (tH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing
of VIH(DC)MIN and the first crossing of VREF(DC). If the actual signal is always later than the nominal slew rate line between
shaded ‘dc level to VREF(DC) region’ use nominal slew rate for derating value. If the actual signal is earlier than the nominal
slew rate line anywhere between shaded ‘dc to VREF(DC) region’, the slew rate of a tangent line to the actual signal from the
dc level to VREF(DC) level is used for derating value.
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