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參數(shù)資料
| 型號(hào)： | IDTSSTE32882HLBBKG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 31/73頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC REGISTERING CLK DRIVER 176BGA |
| 標(biāo)準(zhǔn)包裝： | 208 |
| 類型： | 時(shí)鐘緩沖器/驅(qū)動(dòng)器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 存儲(chǔ)器，DDR3，RDIMM |
| 輸入： | CMOS |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 5:60 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 810MHz |
| 電源電壓： | 1.282 V ~ 1.575 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 176-TFBGA |
| 供應(yīng)商設(shè)備封裝： | 176-CABGA（6x15） |
| 包裝： | 托盤 |
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1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
37
SSTE32882HLB
7201/14
SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE
From a device perspective, the initialization sequence must be as shown in the following Device Initialization table.
SSTE32882HLB Device Initialization Sequence1.
1. x=Logic low or lolgic high. Z=floating.
2. n = 1 for QuadCS disabled mode, n = 3 for QuadCS enabled mode.
3. The feedback clock (FBOUT and FBOUT) pins may or may not be actively driven by the device.
4. The system may power up using either 1.5V or 1.35V. The BIOS reads the SPD and adjusts the voltage if needed from 1.35V to 1.5V or from 1.5V to 1.35V.
After the voltage transition, stable power is provided for a minimum of 200 uS with RESET asserted.
5. QxCKEn and ERROUT will be driven to these logic states by the register after RESET is driven low and VDD is 1.5V or 1.35V (nominal).
6. This indicates the state of QxODTx after RESET switches from low-to-high and before the rising CK edge (falling CK edge). After the first rising CK edge,
within (tSTAB - tACT) us, the state of QxODTx is a function of DODTx (high or low).
7. Step 7 is a typical usage example and is not a register requirement.
Reset Initialization with Stable Power
The timing diagram in the following diagram depicts the initialization sequence with stable power and clock. This will apply to
the situation when we have a soft reset in the system. RESET will be asserted for minimum 100ns. This RESET timing is based
on DDR3 DRAM Reset Initialization with Stable Power requirement, and is a minimum requirement. Actual RESET timing
can vary base on specific system requirement, but it cannot be less than 100ns as required by JESD79-3 Specification.
Step
Power
Inputs: Signals provided by the controller
Outputs: Signals provided by the device
VDD, AVDD,
PVDD
RESET Vref
DCS
[n:0]2
DODT
[0:1]
DCKE
[0:1]
DA/C
PAR_IN
CK,CK
QCS
[n:0]
2
QODT
[0:1]
QCKE
[0:1]
QxA/C ERROUT Y[0:3]
Y[0:3]
FB
OUT3
00V
X or Z
X or
Z
X or Z
X or
Z
X or
Z
X or Z
Z
1
0-->VDD
X or Z
X or
Z
X or Z
X or
Z
X or
Z
X or Z
L
X or
Z
X or Z X or Z X or Z
X or Z
24
VDD
1.5V-->1.35V
1.35V-->1.5V
LX or Z
X or
Z
X or Z
X or
Z
X or
Z
X or Z
L
Z
L5
Z
H5
ZZ
3
VDD
LX or Z
X or
Z
X or Z
X or
Z
X or
Z
X or Z
running
ZZ
LZ
HZ
Z
4
VDD
LX or Z
H
X or Z
L
X or
Z
X or Z
running
Z
LZ
HZ
Z
5
VDD
L
stable
voltage
HX
L
XX
running
Z
LZ
HZ
Z
6
VDD
H
stable
voltage
HX
L
XX
running
H
L6
LX
H
running running
77
VDD
H
stable
voltage
H
X
running
After Step 6 (Step 7 and beyond), the device outputs are as defined in the
device Function Tables.
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