參數(shù)資料
型號(hào)： IDT821054PQF
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 25/45頁(yè)
文件大小： 0K
描述： IC PCM CODEC QUAD MPI 64-PQFP
標(biāo)準(zhǔn)包裝： 84
類型： PCM 編解碼器/濾波器
數(shù)據(jù)接口： PCM 音頻接口
ADC / DAC 數(shù)量： 4 / 4
三角積分調(diào)變： 無(wú)
電壓 - 電源，模擬： 4.75 V ~ 5.25 V
電壓 - 電源，數(shù)字： 4.75 V ~ 5.25 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-QFP
供應(yīng)商設(shè)備封裝： 64-PQFP（14x14）
包裝： 管件
其它名稱： 821054PQF
31
IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
INDUSTRIAL TEMPERATURE RANGE
3.4.3
LOCAL REGISTERS LIST
LREG1: Coefficient Selection, Read/Write (00H/80H)
The Coefficient Select bits (CS[7:0]) are used to control digital filters and function blocks on each channel. The digital filters include
Impedance Matching Filter, Echo Cancellation Filter, High-Pass Filter, Gain for Impedance Scaling, Gain in the Transmit/Receive Path
and Frequency Response Correction in the Transmit/Receive Path. See Figure - 4 on page 11 for details. It should be noted that the
Impedance Matching Filter and Gain for Impedance Scaling are working together to adjust the impedance. So the CS[0] and CS[2] bits
should be set to the same value to ensure proper operation.
CS [7] = 0: The Digital Gain Filter in the Receive path (GRX) is disabled (default);
CS [7] = 1: The Digital Gain in the Receive path (GRX) is programmed by the Coe-RAM.
CS [6] = 0: The Frequency Response Correction filter in the Receive path (FRR) is disabled (default);
CS [6] = 1: The coefficient of the Frequency Response Correction filter in the Receive path (FRR) is programmed by the Coe-RAM.
CS [5] = 0: The Digital Gain Filter in the Transmit path (GTX) is disabled (default);
CS [5] = 1: The Digital Gain in the Transmit path (GTX) is set by the Coe-RAM.
CS [4] = 0: The Frequency Response Correction filter in the Transmit path (FRX) is disabled (default);
CS [4] = 1: The coefficient of the Frequency Response Correction filter in the Transmit path (FRX) is programmed by the Coe-RAM.
CS [3] = 0: The High-Pass Filter (HPF) is bypassed/disabled;
CS [3] = 1: The High-Pass Filter (HPF) is enabled (default).
CS [2] = 0: The Gain for Impedance Scaling filter (GIS) is disabled (default);
CS [2] = 1: The coefficient of the Gain for Impedance Scaling filter (GIS) is programmed by the Coe-RAM.
CS [1] = 0: The Echo Cancellation Filter (ECF) is disabled (default);
CS [1] = 1: The coefficient of the Echo Cancellation Filter (ECF) is programmed by the Coe-RAM.
CS [0] = 0: The Impedance Matching Filter (IMF) is disabled (default);
CS [0] = 1: The coefficient of theImpedance Matching Filter (IMF) is programmed by the Coe-RAM.
LREG2: Local Loopback Control and SLIC Input Interrupt Enable, Read/Write (01H/81H)
The SLIC Input Interrupt Enable bits IE[4:0] enable or disable the interrupt signal on each channel.
IE[4] = 0: Interrupt disabled. The interrupt generated by changes of SB3 (when SB3 is selected as an input) will be ignored (default);
IE[4] = 1: Interrupt enabled. The interrupt generated by changes of SB3 (when SB3 is selected as an input) will be recognized.
IE[3] = 0: Interrupt disabled. The interrupt generated by changes of SB2 (when SB2 is selected as an input) will be ignored (default);
IE[3] = 1: Interrupt enabled. The interrupt generated by changes of SB2 (when SB2 is selected as an input) will be recognized.
IE[2] = 0: Interrupt disabled. The interrupt generated by changes of SB1 (when SB1 is selected as an input) will be ignored (default);
IE[2] = 1: Interrupt enabled. The interrupt generated by changes of SB1 (when SB1 is selected as an input) will be recognized.
IE[1] = 0: Interrupt disabled. The interrupt generated by changes of SI2 will be ignored (default);
IE[1] = 1: Interrupt enabled. The interrupt generated by changes of SI2 will be recognized.
IE[0] = 0: Interrupt disabled. The interrupt generated by changes of SI1 will be ignored (default);
b7
b6
b5
b4
b3
b2
b1
b0
Command
R/W
0
0000
00
I/O data
CS[7]
CS[6]
CS[5]
CS[4]
CS[3]
CS[2]
CS[1]
CS[0]
b7
b6
b5
b4
b3
b2
b1
b0
Command
R/W
0
0000
01
I/O data
IE[4]
IE[3]
IE[2]
IE[1]
IE[0]
DLB_PCM
ALB_1BIT
DLB_1BIT
相關(guān)PDF資料
PDF描述
IDT82V3001APVG8 IC PLL WAN W/SGL REF INP 56-SSOP
IDT82V3010PVG IC PLL WAN 51/E1/OC3 DUAL 56SSOP
IDT82V3011PVG IC PLL WAN T1/E1/OC3 SGL 56-SSOP
IDT82V3012PVG8 IC PLL WAN T1/E1/OC3 DUAL 56SSOP
IDT82V3155PVG IC PLL WAN T1/E1/OC3 DUAL 56SSOP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT821054PQFG 功能描述:IC PCM CODEC QUAD MPI 64-PQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR)
IDT821064 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:QUAD PROGRAMMABLE PCM CODEC WITH GCI INTERFACE
IDT821064PQF 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:QUAD PROGRAMMABLE PCM CODEC WITH GCI INTERFACE
IDT821068 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:OCTAL PROGRAMMABLE PCM CODEC
IDT821068PX 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:OCTAL PROGRAMMABLE PCM CODEC
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*