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| 型號： | IDT821054PQF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 10/45頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCM CODEC QUAD MPI 64-PQFP |
| 標(biāo)準(zhǔn)包裝： | 84 |
| 類型： | PCM 編解碼器/濾波器 |
| 數(shù)據(jù)接口： | PCM 音頻接口 |
| ADC / DAC 數(shù)量： | 4 / 4 |
| 三角積分調(diào)變： | 無 |
| 電壓 - 電源，模擬： | 4.75 V ~ 5.25 V |
| 電壓 - 電源，數(shù)字： | 4.75 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-QFP |
| 供應(yīng)商設(shè)備封裝： | 64-PQFP（14x14） |
| 包裝： | 管件 |
| 其它名稱： | 821054PQF |
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18
IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
INDUSTRIAL TEMPERATURE RANGE
Block 5: FRR RAM (Word 32 - Word 38) and GRX RAM (Word 39),
containing the coefficient of the Frequency Response Correction in
Receive Path and the Gain in Receive Path.
For the Coe-RAM is addressed on a per-channel basis, users should
specify a channel (by setting the corresponding CE bit in GREG6 to ‘1’)
before writing/reading coefficients to/from the Coe-RAM.
To write a Coe-RAM word, 16 bits (b[15:0]) or two 8-bit bytes are
needed to fulfill with MSB first, but the lowest two bits (b[1:0]) will be
ignored. When read, each word will output 16 bits with MSB first, but the
lowest two bits (b[1:0]) are meaningless.
The address in a Coe-RAM command (b[4:0]) specifies a block of
Coe-RAM to be accessed. When a Coe-RAM command is executed, the
CODEC automatically counts down from the highest address to the
lowest address of the specified block. So all 8 words of the block will be
addressed by one Coe-RAM command.
When addressing the Coe-RAM, the procedure of consecutive
adjacent addressing can be stopped by the CS signal at any time. If the
CS signal is changed from low to high, the operation to the current word
and the next adjacent words will be aborted. However, the previous
operation results will not be affected.
3.1.5
ADDRESSING FSK-RAM
The FSK-RAM consists of 4 blocks, and each block has 8 16-bit
words. The total 32 words (i.e. 64 bytes) of FSK-RAM are shared by all
four channels and only one channel can use it at one time.
To write a FSK-RAM word, 16 bits (or, two 8-bit bytes) are needed to
fulfill with MSB first. When being read, each FSK-RAM word in FSK-
RAM will output 16 bits with MSB first.
When addressing the FSK-RAM, the b3 bit in a FSK-RAM Command
should be ‘0’ and the b4 bit should be ‘1’, the b[2:0] bits specify one of
the 4 blocks of FSK-RAM. Then, all 8 words of the specified block will be
addressed automatically, with the highest order word first.
3.1.6
PROGRAMMING EXAMPLES
3.1.6.1 Example of Programming Local Registers
Writing to LREG2 and LREG1 of Channel 1:
1010, 0101
Channel Enable command
0001, 0010
Data for GREG6 (Channel 1 is enabled for programming)
1000, 0001
Local register write command (The address is '00001', which means that data will be written to LREG2 and LREG1.)
xxxx, xxxx
Data for LREG2
xxxx, xxxx
Data for LREG1
Reading from LREG2 and LREG1 of Channel 1:
1010, 0101
Channel Enable command
0001, 0010
Data for GREG6 (Channel 1 is enabled for programming)
0000, 0001
Local register read command (The address is '00001', which means that LREG2 and LREG1 will be read.)
After the preceding commands are executed, data will be sent out as follows:
1000, 0001
Identification code
xxxx, xxxx
Data read out from LREG2
xxxx, xxxx
Data read out from LREG1
3.1.6.2 Example of Programming Global Registers
Writing to GREG1:
1010, 0000
Global register write command (The address is '00000', which means that data will be written to GREG1.)
1111, 1111
Data for GREG1
Reading from GREG1:
0010, 0000
Global register read command (The address is '00000', which means that GREG1 will be read.)
After the preceding command is executed, data will be sent out as follows:
1000, 0001
Identification code
0000, 0001
Data read out from GREG1
3.1.6.3 Example of Programming the Coefficient-RAM
Writing to the Coe-RAM
1010,0101
Channel Enable command
0001,0010
Data for GREG6 (Channel 1 is enabled for programming)
1110,0010
Coe-RAM write command (The address of '00010' is located in block 3, which means that data will be written to block 3.)
data byte 1
high byte of word 8 of block 3
data byte 2
low byte of word 8 of block 3
data byte 3
high byte of word 7 of block 3
data byte 4
low byte of word 7 of block 3
data byte 5
high byte of word 6 of block 3
data byte 6
low byte of word 6 of block 3
data byte 7
high byte of word 5 of block 3
data byte 8
low byte of word 5 of block 3
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT821054PQFG | 功能描述:IC PCM CODEC QUAD MPI 64-PQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
| IDT821064 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:QUAD PROGRAMMABLE PCM CODEC WITH GCI INTERFACE |
| IDT821064PQF | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:QUAD PROGRAMMABLE PCM CODEC WITH GCI INTERFACE |
| IDT821068 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:OCTAL PROGRAMMABLE PCM CODEC |
| IDT821068PX | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:OCTAL PROGRAMMABLE PCM CODEC |
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