參數(shù)資料
型號(hào): IDT821054PQF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 15/45頁
文件大小: 0K
描述: IC PCM CODEC QUAD MPI 64-PQFP
標(biāo)準(zhǔn)包裝: 84
類型: PCM 編解碼器/濾波器
數(shù)據(jù)接口: PCM 音頻接口
ADC / DAC 數(shù)量: 4 / 4
三角積分調(diào)變:
電壓 - 電源,模擬: 4.75 V ~ 5.25 V
電壓 - 電源,數(shù)字: 4.75 V ~ 5.25 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-QFP
供應(yīng)商設(shè)備封裝: 64-PQFP(14x14)
包裝: 管件
其它名稱: 821054PQF
22
IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
INDUSTRIAL TEMPERATURE RANGE
3.4
REGISTERS DESCRIPTION
3.4.1
REGISTERS OVERVIEW
Table - 3 Global Registers (GREG) Mapping
Name
Function
Register Byte
Read
Command
Write
Command
Default
Value
b7
b6
b5
b4
b3
b2
b1
b0
GREG1
Version number (read)/
no operation (write)
20H
A0H
01H
GREG2
Interrupt clear
A1H
GREG3
Software reset
A2H
GREG4
Hardware reset
A3H
GREG5
Chopper clock selection
Reserved
CHclk2[1] CHclk2[0] CHclk1[3] CHclk1[2] CHclk1[1] CHclk1[0]
24H
A4H
00H
GREG6
MCLK selection and
channel program enable
CE[3]
CE[2]
CE[1]
CE[0]
Sel[3]
Sel[2]
Sel[1]
Sel[0]
25H
A5H
02H
GREG7
Data format,
companding law, clock
slope and PCM delay
time selection
A-
VDS
CS[2]
CS[1]
CS[0]
OC[2]
OC[1]
OC[0]
26H
A6H
00H
GREG8
SLIC ring trip setting
and control
OPI
Reserved
IPI
IS
RTE
OS[2]
OS[1]
OS[0]
27H
A7H
00H
GREG9
Debounced data on SI1
and SI2 pins
SIB[3]
SIB[2]
SIB[1]
SIB[0]
SIA[3]
SIA[2]
SIA[1]
SIA[0]
28H
00H
GREG10
SB1 direction control
and SB1 data
SB1C[3]
SB1C[2]
SB1C[1]
SB1C[0]
SB1[3]
SB1[2]
SB1[1]
SB1[0]
29H
A9H
00H
GREG11
SB2 direction control
and SB2 data
SB2C[3]
SB2C[2]
SB2C[1]
SB2C[0]
SB2[3]
SB2[2]
SB2[1]
SB2[0]
2AH
AAH
00H
GREG12
SB3 direction control
and SB3 data
SB3C[3]
SB3C[2]
SB3C[1]
SB3C[0]
SB3[3]
SB3[2]
SB3[1]
SB3[0]
2BH
ABH
00H
GREG13
FSK Flag Length
FL[7]
FL[6]
FL[5]
FL[4]
FL[3]
FL[2]
FL[1]
FL[0]
2CH
ACH
00H
GREG14
FSK Data Length
DL[7]
DL[6]
DL[5]
DL[4]
DL[3]
DL[2]
DL[1]
DL[0]
2DH
ADH
00H
GREG15
FSK Seizure Length
SL[7]
SL[6]
SL[5]
SL[4]
SL[3]
SL[2]
SL[1]
SL[0]
2EH
AEH
00H
GREG16
FSK Mark Length
ML[7]
ML[6]
ML[5]
ML[4]
ML[3]
ML[2]
ML[1]
ML[0]
2FH
AFH
00H
GREG17
FSK configuration
Reserved
FCS[1]
FCS[0]
FO
BS
MAS
FS
30H
B0H
00H
GREG18
Level meter result low
byte
LVLL[7]
LVLL[6]
LVLL[5]
LVLL[4]
LVLL[3]
LVLL[2]
LVLL[1]
LVLL[0]
31H
00H
GREG19
Level meter result high
byte
LVLH[7]
LVLH[6]
LVLH[5]
LVLH[4]
LVLH[3]
LVLH[2]
LVLH[1]
LVLH[0]
32H
00H
GREG20
Level meter count
number
CN[7]
CN[6]
CN[5]
CN[4]
CN[3]
CN[2]
CN[1]
CN[0]
33H
B3H
00H
GREG21
level meter mode and
channel selection, level
meter enable
Reserved
LMO
L/C
CS[1]
CS[0]
34H
B4H
00H
GREG22
Loopback control and
PLL power down
Reserved
PPD
DLB_ANA ALB_8k
DLB_8k
DLB_DI
ALB_DI
35H
B5H
00H
GREG23
Over-sampling timing
tuning
37H
B7H
00H
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