- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄299202 > IDT79RC32V332-100DPI (INTEGRATED DEVICE TECHNOLOGY INC) 32-BIT, 100 MHz, RISC MICROCONTROLLER, PQFP208 PDF資料下載
參數(shù)資料
| 型號： | IDT79RC32V332-100DPI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 100 MHz, RISC MICROCONTROLLER, PQFP208 |
| 封裝： | 28 X 28 MM, 3.40 MM HEIGHT, PLASTIC, QFP-208 |
| 文件頁數(shù)： | 27/27頁 |
| 文件大?。?/td> | 246K |
| 代理商： | IDT79RC32V332-100DPI |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁當(dāng)前第27頁
9 of 27
September 14, 2001
79RC32332
cpu_coldreset_n
Input
—
CPU Cold Reset
This active-low signal is asserted to the RC32332 after
Vcc becomes valid on the initial power-up. The Reset
initialization vectors for the RC32332 are latched by cold reset.
cpu_dt_r_n
Output
—
CPU Direction Transmit/Receive
This active-low signal controls the DT/R pin of an optional FCT245 transceiver bank. It is asserted during read
operations.
1st Alternate function: mem_245_dt_r_n.
2nd Alternate function: sdram_245_dt_r_n.
JTAG Interface Signals
jtag_tck
Input
—
JTAG Test Clock Requires an external pull-down.
An input test clock used to shift into or out of the Boundary-Scan register cells. jtag_tck is independent of the
system and the processor clock with nominal 50% duty cycle.
jtag_tdi,
ejtag_dint_n
Input
—
JTAG Test Data In Requires an external pull-up.
On the rising edge of jtag_tck, serial input data are shifted into either the Instruction or Data register, depend-
ing on the TAP controller state. During Real Mode, this input is used as an interrupt line to stop the debug unit
from Real Time mode and return the debug unit back to Run Time Mode (standard JTAG). This pin is also
used as the ejtag_dint_n signal in the EJTAG mode.
jtag_tdo,
ejtag_tpc
Output
High
JTAG Test Data Out
The jtag_tdo is serial data shifted out from instruction or data register on the falling edge of jtag_tck. When no
data is shifted out, the jtag_tdo is tri-stated. During Real Time Mode, this signal provides a non-sequential
program counter at the processor clock or at a division of processor clock. This pin is also used as the
ejtag_tpc signal in the EJTAG mode.
jtag_tms
Input
—
JTAG Test Mode Select Requires an external pull-up.
The logic signal received at the jtag_tms input is decoded by the TAP controller to control test operation.
jtag_tms is sampled on the rising edge of the jtag_tck.
jtag_trst_n
Input
—
JTAG Test Reset
The jtag_trst_n pin is an active-low signal for asynchronous reset of the debug unit, independent of the pro-
cessor logic. An external pull-up on the board is recommended to meet the JTAG specification in cases
where the tester can not access this signal, however, specific systems ordinarily should either
1) drive low this signal
2) use an external pulldown on the board
3) clock jtag_tclk
ejtag_dclk
Output
—
EJTAG Test Clock
Processor Clock. During Real Time Mode, this signal is used to capture address and data from the ejtag_tpc
signal at the processor clock speed or any division of the internal pipeline.
ejtag_pcst[2:0]
I/O
Low
EJTAG PC Trace Status Information
111 (STL) Pipe line Stall
110 (JMP) Branch/Jump forms with PC output
101 (BRT) Branch/Jump forms with no PC output
100 (EXP) Exception generated with an exception vector code output
011 (SEQ) Sequential performance
010 (TST) Trace is outputted at pipeline stall time
001 (TSQ) Trace trigger output at performance time
000 (DBM) Run Debug Mode
Alternate function: modebit[2:0].
Name
Type
Drive
Strength
Capability
Description
Table 1 Pin Descriptions (Part 5 of 6)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT79RC3610033MS | 32-BIT, 33 MHz, RISC MICROCONTROLLER, PQFP208 |
| IDT7M7025SXXCH | SPECIALTY MEMORY CIRCUIT, CPGA66 |
| IDT7MB6039S25K | 32K X 60 CACHE SRAM MODULE, 25 ns, QMA128 |
| IDTQS3162214PV | 12-BIT EXCHANGER, TRUE OUTPUT, PDSO56 |
| IDTQS32XV245Q2G | CBT/FST/QS/5C/B SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO40 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT79RC32V332-133DH | 功能描述:IC PROC 32BIT CPU 133MHZ 208-QFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:Interprise™ 標(biāo)準(zhǔn)包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點:- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應(yīng)商設(shè)備封裝:357-PBGA（25x25） 包裝:托盤 |
| IDT79RC32V332-133DHG | 功能描述:IC PROC 32BIT CPU 133MHZ 208-QFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:Interprise™ 標(biāo)準(zhǔn)包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點:- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應(yīng)商設(shè)備封裝:357-PBGA（25x25） 包裝:托盤 |
| IDT79RC32V332-133DHGI | 制造商:Integrated Device Technology Inc 功能描述:IC PROC 32BIT CPU 133MHZ 208-QFP |
| IDT79RC32V332-133DHI | 功能描述:IC PROC 32BIT CPU 133MHZ 208-QFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:Interprise™ 標(biāo)準(zhǔn)包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點:- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應(yīng)商設(shè)備封裝:357-PBGA（25x25） 包裝:托盤 |
| IDT79RC32V332-150DH | 功能描述:IC PROC 32BIT CPU 150MHZ 208-QFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:Interprise™ 標(biāo)準(zhǔn)包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點:- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應(yīng)商設(shè)備封裝:357-PBGA（25x25） 包裝:托盤 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。