參數(shù)資料
型號(hào): IDT79RC32V332-100DPI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 100 MHz, RISC MICROCONTROLLER, PQFP208
封裝: 28 X 28 MM, 3.40 MM HEIGHT, PLASTIC, QFP-208
文件頁(yè)數(shù): 25/27頁(yè)
文件大?。?/td> 246K
代理商: IDT79RC32V332-100DPI
7 of 27
September 14, 2001
79RC32332
pci_req_n[0]
I/O
High
PCI Bus Request #0 Negated Requires an external pull-up for burst mode.
Host mode: pci_req_n[0] is an input indicating a request from an external device.
Satellite mode: pci_req_n[0] is an output indicating a request from this device.
pci_gnt_n[2]
Output
High
PCI Bus Grant #2 Negated Recommend an external pull-up.
Host mode: pci_gnt_n[2] is an output indicating a grant to an external device.
Satellite mode: pci_gnt_n[2] is used as the pci_inta_n output pin. External pull-up is required.
Alternate function: pci_inta_n (satellite).
pci_gnt_n[1]
I/O
High
PCI Bus Grant #1 Negated Recommend an external pull-up.
Host mode: not used.
Satellite mode: Used as pci_eprom_cs output pin for Serial Chip Select for loading PCI Configuration Regis-
ters in the RC32332 Reset Initialization Vector PCI boot mode. Defaults to the output direction at reset time.
1st Alternate function: pci_eeprom_cs (satellite).
2nd Alternate function: PIO[7].
pci_gnt_n[0]
I/O
High
PCI Bus Grant #0 Negated
Host mode: pci_gnt_n[0] is an output indicating a grant to an external device. Recommend external pull-up.
Satellite mode: pci_gnt_n[0] is an input indicating a grant to this device. Requires external pull-up.
pci_inta_n
Output
Open-
collector
PCI
PCI Interrupt #A Negated
Uses pci_gnt_n[2]. See the PCI subsection.
pci_lock_n
Input
PCI Lock Negated
Driven by the Bus Master to indicate that an exclusive operation is occurring.
SDRAM Control Interface
sdram_addr_12
Output
High
SDRAM Address Bit 12 and Precharge All
SDRAM mode: Provides SDRAM address bit 12 (10 on the SDRAM chip) during row address and "precharge
all" signal during refresh, read and write command.
sdram_ras_n
Output
High
SDRAM RAS Negated
SDRAM mode: Provides SDRAM RAS control signal to all SDRAM banks.
sdram_cas_n
Output
High
SDRAM CAS Negated
SDRAM mode: Provides SDRAM CAS control signal to all SDRAM banks.
sdram_we_n
Output
High
SDRAM WE Negated
SDRAM mode: Provides SDRAM WE control signal to all SDRAM banks.
sdram_cke
Output
High
SDRAM Clock Enable
SDRAM mode: Provides clock enable to all SDRAM banks.
sdram_cs_n[3:0]
Output
High
SDRAM Chip Select Negated Bus Recommend an external pull-up.
SDRAM mode: Provides chip select to each SDRAM bank.
SODIMM mode: Provides upper select byte enables [7:4].
sdram_s_n[1:0]
Output
High
SDRAM SODIMM Select Negated Bus
SDRAM mode: Not used.
SDRAM SODIMM mode: Upper and lower chip selects.
sdram_bemask_n[3:0] Output
High
SDRAM Byte Enable Mask Negated Bus (DQM)
SDRAM mode: Provides byte enables for each byte lane of all DRAM banks.
SODIMM mode: Provides lower select byte enables [3:0].
sdram_245_oe_n
Output
Low
SDRAM FCT245 Output Enable Negated Recommend an external pull-up.
SDRAM mode: Controls output enable to optional FCT245 transceiver bank by asserting during both reads
and writes to any DRAM bank.
sdram_245_dt_r_n
Output
High
SDRAM FCT245 Direction Transmit/Receive Recommend an external pull-up.
Uses cpu_dt_r_n. See CPU Core Specific Signals below.
Name
Type
Drive
Strength
Capability
Description
Table 1 Pin Descriptions (Part 3 of 6)
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