- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4021 > IDT79RC32T351-133DH (IDT, Integrated Device Technology Inc)IC MPU 32BIT CORE 133MHZ 208-QFP PDF資料下載
參數(shù)資料
| 型號： | IDT79RC32T351-133DH |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 42/42頁 |
| 文件大小： | 0K |
| 描述： | IC MPU 32BIT CORE 133MHZ 208-QFP |
| 產(chǎn)品變化通告： | Product Discontinuation 07/Dec/2009 |
| 標準包裝： | 24 |
| 系列： | Interprise™ |
| 處理器類型： | RISC 32-位 |
| 速度： | 133MHz |
| 電壓： | 2.5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 208-BFQFP |
| 供應商設備封裝： | 208-PQFP（28x28） |
| 包裝： | 托盤 |
| 其它名稱： | 79RC32T351-133DH |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁當前第42頁
9 of 42
May 25, 2004
IDT 79RC32351
MIIMDIOP
I/O
Low Drive
with STI
MII Management Data. This bidirectional signal is used to transfer data between the station management entity and the
ethernet PHY.
MIIRXCLKP
I
STI
MII Receive Clock. This clock is a continuous clock that provides a timing reference for the reception of data.
MIIRXDP[3:0]
I
STI
MII Receive Data. This nibble wide data bus contains the data received by the ethernet PHY.
MIIRXDVP
I
STI
MII Receive Data Valid. The assertion of this signal indicates that valid receive data is in the MII receive data bus.
MIIRXERP
I
STI
MII Receive Error. The assertion of this signal indicates that an error was detected somewhere in the ethernet frame cur-
rently being sent in the MII receive data bus.
MIITXCLKP
I
STI
MII Transmit Clock. This clock is a continuous clock that provides a timing reference for the transfer of transmit data.
MIITXDP[3:0]
O
Low Drive MII Transmit Data. This nibble wide data bus contains the data to be transmitted.
MIITXENP
O
Low Drive MII Transmit Enable. The assertion of this signal indicates that data is present on the MII for transmission.
MIITXERP
O
Low Drive MII Transmit Coding Error. When this signal is asserted together with MIITXENP, the ethernet PHY will transmit symbols
which are not valid data or delimiters.
EJTAG
JTAG_TCK
I
STI
JTAG Clock. This is an input test clock, used to shift data into or out of the boundary scan logic. This signal requires an
external resistor, listed in Table 14.
JTAG_TDI
I
STI
JTAG Data Input. This is the serial data shifted into the boundary scan logic. This signal requires an external resistor,
listed in Table 14. This is also used to input EJTAG_DINTN during EJTAG/ICE mode. EJTAG_DINTN is an interrupt to
switch the PC trace mode off.
JTAG_TDO
O
Low Drive JTAG Data Output. This is the serial data shifted out from the boundary scan logic. When no data is being shifted out, this
signal is tri-stated. This signal requires an external resistor, listed in Table 14. This is also used to output the EJTAG_TPC
during EJTAG/ICE mode. EJTAG_TPC is the non-sequential program counter output.
JTAG_TMS
I
STI
JTAG Mode Select. This input signal is decoded by the tap controller to control test operation. This signal requires an
external resistor, listed in Table 14.
EJTAG_PCST[0]
O
Low Drive PC trace status. This bus gives the PC trace status information during EJTAG/ICE mode. EJTAG/ICE enable is selected
during reset using the boot configuration and overrides the selection of the Primary and Alternate functions. This signal
requires an external resistor, listed in Table 14.
Primary function: General Purpose I/O, GPIOP[10].
1st Alternate function: UART channel 1 data terminal ready, U1DTRN.
EJTAG_PCST[1]
O
Low Drive PC trace status. This bus gives the PC trace status information during EJTAG/ICE mode. EJTAG/ICE enable is selected
during reset using the boot configuration and overrides the selection of the Primary and Alternate functions. This signal
requires an external resistor, listed in Table 14.
Primary function: General Purpose I/O, GPIOP[11]. At reset, this pin defaults to primary function GPIOP[11].
1st Alternate function: UART channel 1 data set ready, U1DSRN.
EJTAG_PCST[2]
O
Low Drive PC trace status. This bus gives the PC trace status information during EJTAG/ICE mode. EJTAG/ICE enable is selected
during reset using the boot configuration and overrides the selection of the Primary and Alternate functions. This signal
requires an external resistor, listed in Table 14.
Primary function: General Purpose I/O, GPIOP[12].
1st Alternate function: UART channel 1 request to send, U1RTSN.
EJTAG_DCLK
O
Low Drive PC trace clock. This is used to capture address and data during EJTAG/ICE mode. EJTAG/ICE enable is selected during
reset using the boot configuration and overrides the selection of the Primary and Alternate functions. This signal requires
an external resistor, listed in Table 14.
Primary function: General Purpose I/O, GPIOP[13].
1st Alternate function: UART channel 1 clear to send, U1CTSN.
Name
Type I/O Type
Description
Table 1 Pin Descriptions (Part 5 of 7)
相關PDF資料 |
PDF描述 |
|---|---|
| IDT79RC32T351-100DHG | IC MPU 32BIT CORE 100MHZ 208-QFP |
| IDT79RC32T351-100DH | IC MPU 32BIT CORE 100MHZ 208-QFP |
| IDT79RC32T333-150DH | IC MPU 32BIT CORE 150MHZ 208-QFP |
| IDT79RC32T333-133DHI | IC MPU 32BIT CORE 133MHZ 208-QFP |
| IDT71T75802S166BGI | IC SRAM 18MBIT 166MHZ 119BGA |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IDT79RC32T351-133DHG | 功能描述:IC MPU 32BIT CORE 133MHZ 208-QFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:Interprise™ 標準包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點:- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應商設備封裝:357-PBGA（25x25） 包裝:托盤 |
| IDT79RC32T355-100DHGI | 制造商:Integrated Device Technology Inc 功能描述:IC MPU 32BIT CORE 100MHZ 208-QFP |
| IDT79RC32T355-133DH | 功能描述:IC MPU 32BIT CORE 133MHZ 208-QFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:Interprise™ 標準包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點:- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應商設備封裝:357-PBGA（25x25） 包裝:托盤 |
| IDT79RC32T355-133DHG | 功能描述:IC MPU 32BIT CORE 133MHZ 208-QFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:Interprise™ 標準包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點:- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應商設備封裝:357-PBGA（25x25） 包裝:托盤 |
| IDT79RC32T355133DHGI | 制造商:IDT 功能描述:Pb Free |
發(fā)布緊急采購，3分鐘左右您將得到回復。