參數(shù)資料
型號: IDT79RC32T351-100DHG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 1/42頁
文件大?。?/td> 0K
描述: IC MPU 32BIT CORE 100MHZ 208-QFP
產(chǎn)品變化通告: Product Discontinuation 07/Dec/2009
標(biāo)準(zhǔn)包裝: 24
系列: Interprise™
處理器類型: RISC 32-位
速度: 100MHz
電壓: 2.5V
安裝類型: 表面貼裝
封裝/外殼: 208-BFQFP
供應(yīng)商設(shè)備封裝: 208-PQFP(28x28)
包裝: 托盤
其它名稱: 79RC32T351-100DHG
1 of 42
May 25, 2004
2002 Integrated Device Technology, Inc.
DSC 6053
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
Features List
RC32300 32-bit Microprocessor
– Enhanced MIPS-II ISA
– Enhanced MIPS-IV cache prefetch instruction
– DSP Instructions
– MMU with 16-entry TLB
– 8kB Instruction cache, 2-way set associative
– 2kB Data cache, 2-way set associative
– Per line cache locking
– Write-through and write-back cache management
– Debug interface through the EJTAG port
– Big or little endian support
Interrupt Controller
– Allows status of each interrupt to be read and masked
UARTs
– Two 16550 Compatible UARTs
– Baud rate support up to 1.5 Mb/s
Counter/Timers
– Three general purpose 32-bit counter/timers
General Purpose I/O Pins (GPIOP)
– 32 individually programmable pins:
each pin programmable as input, output, or alternate function,
input can be an interrupt or NMI source,
input can also be active high or active low
– 4 additional, auxiliary GPIO pins can be configured as input or
output
SDRAM Controller
– 2 memory banks, non-interleaved, 512 MB total
– 32-bit wide data path
– Supports 4-bit, 8-bit, and 16-bit wide SDRAM chips
– SODIMM support
– Stays on page between transfers
– Automatic refresh generation
Peripheral Device Controller
– 26-bit address bus
– 32-bit data bus with variable width support of 8-,16-, or 32-bits
– 8-bit boot ROM support
– 6 banks available, up to 64MB per bank
– Supports Flash ROM, PROM, SRAM, dual-port memory, and
peripheral devices
– Supports external wait-state generation, Intel or Motorola style
– Write protect capability
– Direct control of optional external data transceivers
System Integrity
– Programmable system watchdog timer resets system on time-
out
– Programmable bus transaction times memory and peripheral
transactions and generates a warm reset on time-out
DMA
– 14 DMA channels
– Services on-chip and external peripherals
– Supports memory-to-memory, memory-to-I/O, and I/O-to-I/O
transfers
– Supports flexible descriptor based operation and chaining via
linked lists of records (scatter / gather capability)
– Supports unaligned transfers
Block Diagram
EJTAG
MMU
D. Cache
I. Cache
RC32300
CPU Core
ICE
Interrupt
Controller
3 Counter
Timers
Watchdog
Timer
10/100
Ethernet
Interface
USB
Interface
16 Channel
DMA
Controller
Arbiter
Ext. Bus
Master
SDRAM &
Device
Controller
2 UARTS
(16550)
GPIO
Interface
ATM
Interface
Memory &
Peripheral Bus
Ch. 1 Ch. 2
Serial Channels
GPIO Pins
Utopia 1 / 2
:
79RC32351
IDTTM InterpriseTM Integrated
Communications Processor
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