參數(shù)資料
型號： IDT79RC32T351-100DHG
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 38/42頁
文件大?。?/td> 0K
描述： IC MPU 32BIT CORE 100MHZ 208-QFP
產品變化通告： Product Discontinuation 07/Dec/2009
標準包裝： 24
系列： Interprise™
處理器類型： RISC 32-位
速度： 100MHz
電壓： 2.5V
安裝類型： 表面貼裝
封裝/外殼： 208-BFQFP
供應商設備封裝： 208-PQFP（28x28）
包裝： 托盤
其它名稱： 79RC32T351-100DHG
5 of 42
May 25, 2004
IDT 79RC32351
Pin Description Table
The following table lists the functions of the pins provided on the RC32351. Some of the functions listed may be multiplexed onto the same pin.
To define the active polarity of a signal, a suffix will be used. Signals ending with an “N” should be interpreted as being active, or asserted, when at
a logic zero (low) level. All other signals (including clocks, buses and select lines) will be interpreted as being active, or asserted when at a logic one
(high) level.
Note: The input pads of the RC32351 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels.
This is especially critical for unused control signal inputs (such as BRN) which, if left floating, could adversely affect the RC32351’s opera-
tion. Also, any input pin left floating can cause a slight increase in power consumption.
Name
Type I/O Type
Description
System
CLKP
I
Input
System Clock input. This is the system master clock input. The RISCore 32300 pipeline frequency is a multiple (x2, x3, or
x4) of this clock frequency. All other logic runs at this frequency or less.
COLDRSTN
I
STI1
Cold Reset. The assertion of this signal low initiates a cold reset. This causes the RC32351 state to be initialized, boot
configuration to be loaded, and the internal processor PLL to lock onto the system clock (CLKP).
RSTN
I/O
Low Drive
with STI
Reset. This bidirectional signal is either driven low or tri-stated, an external pull-up is required to supply the high state. The
RC32351 drives RSTN low during a reset (to inform the external system that a reset is taking place) and then tri-states it.
The external system can drive RSTN low to initiate a warm reset, and then should tri-state it.
SYSCLKP
O
High Drive System clock output. This is a buffered and delayed version of the system clock input (CLKP). All SDRAM transactions
are synchronous to this clock. This pin should be externally connected to the SDRAMs and to the RC32351 SDCLKINP pin
(SDRAM clock input).
Memory and Peripheral Bus
MADDR[25:0]
O
[21:0] High
Drive
[25:22] Low
Drive with
STI
Memory Address Bus. 26-bit address bus for memory and peripheral accesses. MADDR[20:17] are used for the
SODIMM data mask enables if SODIMM mode is selected.
MADDR[22] Primary function: General Purpose I/O, GPIOP[27].
MADDR[23] Primary function: General Purpose I/O, GPIOP[28].
MADDR[24] Primary function: General Purpose I/O, GPIOP[29].
MADDR[25] Primary function: General Purpose I/O, GPIOP[30].
MDATA[31:0]
I/O
High Drive Memory Data Bus. 32-bit data bus for memory and peripheral accesses.
BDIRN
O
High Drive External Buffer Direction. External transceiver direction control for the memory and peripheral data bus, MDATA[31:0]. It
is asserted low during any read transaction, and remains high during write transactions.
BOEN[1:0]
O
High Drive External Buffer Output Enable. These signals provide two output enable controls for external data bus transceivers on
the memory and peripheral data bus, MDATA. BOEN[0] is asserted low during external device read transactions. BOEN[1]
is asserted low during SDRAM read transactions.
BRN
I
STI
External Bus Request. This signal is asserted low by an external master device to request ownership of the memory and
peripheral bus.
BGN
O
Low Drive External Bus Grant. This signal is asserted low by RC32351 to indicate that RC32351 has relinquished ownership of the
local memory and peripheral bus to an external master.
WAITACKN
I
STI
Wait or Transfer Acknowledge. When configured as wait, this signal is asserted low during a memory and peripheral
device bus transaction to extend the bus cycle. When configured as transfer acknowledge, this signal is asserted low dur-
ing a memory and peripheral device bus transaction to signal the completion of the transaction.
CSN[5:0]
O
[3:0]
High Drive
[5:4]
Low Drive
Device Chip Select. These signals are used to select an external device on the memory and peripheral bus during device
transactions. Each bit is asserted low during an access to the selected external device.
CSN[4] Primary function: General purpose I/O, GPIOP[16].
CSN[5] Primary function: General purpose I/O, GPIOP[17].
Table 1 Pin Descriptions (Part 1 of 7)
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