參數(shù)資料
型號(hào): IDT79RC32T333-150DH
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 1/30頁(yè)
文件大?。?/td> 0K
描述: IC MPU 32BIT CORE 150MHZ 208-QFP
產(chǎn)品變化通告: Product Discontinuation 07/Dec/2009
標(biāo)準(zhǔn)包裝: 24
系列: Interprise™
處理器類型: RISC 32-位
速度: 150MHz
電壓: 2.5V
安裝類型: 表面貼裝
封裝/外殼: 208-BFQFP
供應(yīng)商設(shè)備封裝: 208-PQFP(28x28)
包裝: 托盤
其它名稱: 79RC32T333-150DH
1 of 30
May 4, 2004
2004 Integrated Device Technology, Inc.
DSC 6402
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
IDTTM InterpriseTM Integrated
Communications Processor
3.3V and 2.5V Devices
Device Overview
The RC32333 device is a member of the IDT Interprise family of
integrated communications processors. This product incorporates a
high-performance, low-cost 32-bit CPU core with functionality common
to a large number of embedded applications. The RC32333 integrates
these functions to enable the use of low-cost PC commodity market
memory and I/O devices, allowing the aggressive price/performance
characteristics of the CPU to be realized quickly into low-cost systems.
The RC32333 device is available with either a 3.3V or 2.5V operating
voltage. Differences between the two versions are noted where appli-
cable.
Features
RC32300 32-bit Microprocessor
– Up to 150 MHz operation
– Enhanced MIPS-II Instruction Set Architecture (ISA)
– Cache prefetch instruction
– Conditional move instruction
– DSP instructions
– Supports big or little endian operation
– MMU with 32 page TLB
– 8KB Instruction Cache, 2-way set associative
– 2KB Data Cache, 2-way set associative
– Cache locking per line
– Programmable on a page basis to implement a write-through
no write allocate, write-through write allocate, or write-back
algorithms for cache management
– Compatible with a wide variety of operating systems
Local Bus Interface
– Up to 75 MHz operation
– 23-bit address bus
– 32-bit data bus
– Direct control of local memory and peripherals
– Programmable system watch-dog timers
– Big or little endian support
Interrupt Controller simplifies exception management
Four general purpose 32-bit timer/counters
Programmable I/O (PIO)
– Input/Output/Interrupt source
– Individually programmable
SDRAM Controller (32-bit memory only)
– 4 banks, non-interleaved
– Up to 512MB total SDRAM memory supported
– Implements full, direct control of discrete, SODIMM, or DIMM
memories
– Supports 16Mb through 512Mb SDRAM device depths
– Automatic refresh generation
Block Diagram
Figure 1 RC32333 Block Diagram
Local
Memory/IO
Control
Interrupt Control
DMA Control
UART
32-bit Timers
SPI Control
Programmable I/O
PCI Bridge
IDT
Peripheral
Bus
RISCore 32300
Enhanced MIPS-II ISA
Integer CPU
RC5000
Compatible
CP0
32-page
TLB
EJTAG
In-Circuit Emulator Interface
2KB
2-set, Lockable
Data Cache
8KB
2-set
Lockable
Instr. Cache
IPBus
Bridge
SDRAM
Control
79RC32333
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