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參數(shù)資料
| 型號： | IDT79RC32T333-150DH |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 12/30頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU 32BIT CORE 150MHZ 208-QFP |
| 產(chǎn)品變化通告： | Product Discontinuation 07/Dec/2009 |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | Interprise™ |
| 處理器類型： | RISC 32-位 |
| 速度： | 150MHz |
| 電壓： | 2.5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 208-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 208-PQFP（28x28） |
| 包裝： | 托盤 |
| 其它名稱： | 79RC32T333-150DH |
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May 4, 2004
IDT 79RC32333
◆
Serial Peripheral Interface (SPI) master mode interface
◆
UART Interface
– 16550 compatible UART
– Baud rate support up to 1.5 Mb/s
◆
Memory & Peripheral Controller
– 6 banks, up to 8MB per bank
– Supports 8-,16-, and 32-bit interfaces
– Supports Flash ROM, SRAM, dual-port memory, and
peripheral devices
– Supports external wait-state generation
– 8-bit boot PROM support
– Flexible I/O timing protocols
◆
4 DMA Channels
– 4 general purpose DMA, each with endianess swappers and
byte lane data alignment
– Supports scatter/gather, chaining via linked lists of records
– Supports memory-to-memory, memory-to-I/O, memory-to-
PCI, PCI-to-PCI, and I/O-to-I/O transfers
– Supports unaligned transfers
– Supports burst transfers
– Programmable DMA bus transactions burst size
(up to 16 bytes)
◆
PCI Bus Interface
– 32-bit PCI, up to 50 MHz
– Revision 2.2 compatible
– Target or master
– Host or satellite
– Three slot PCI arbiter
– Serial EEPROM support, for loading configuration registers
◆
Off-the-shelf development tools
◆
JTAG Interface (IEEE Std. 1149.1 compatible)
◆
208 QFP Package
◆
3.3V or 2.5V core supply with 3.3V I/O supply
– 3.3V core supply is 5V I/O tolerant
◆
EJTAG in-circuit emulator interface
CPU Execution Core
The RC32333 integrates the RISCore 32300, the same CPU core
found in the award-winning RC32364 microprocessor. The RISCore
32300 implements the Enhanced MIPS-II ISA. Thus, it is upwardly
compatible with applications written for a wide variety of MIPS architec-
ture processors, and it is kernel compatible with the modern operating
systems that support IDT’s 64-bit RISController product family. The
RISCore 32300 was explicitly defined and designed for integrated
processor products such as the RC32333. Key attributes of the execu-
tion core found within this product include:
◆
High-speed, 5-stage scalar pipeline executes to 150MHz. This
high performance enables the RC32333 to perform a variety of
performance intensive tasks, such as routing, DSP algorithms,
etc.
◆
32-bit architecture with enhancements of key capabilities. Thus,
the RC32333 can execute existing 32-bit programs, while
enabling designers to take advantage of recent advances in
CPU architecture.
◆
Count leading-zeroes/ones. These instructions are common to a
wide variety of tasks, including modem emulation, voice over IP
compression and decompression, etc.
◆
Cache PREFetch instruction support, including a specialized
form intended to help memory coherency. System programmers
can allocate and stage the use of memory bandwidth to achieve
maximum performance.
◆
8KB of 2-way set associative instruction cache
Figure 2 RC32333 Based System Diagram
SDRAM
FLASH
Local I/O
Serial
EEPROM
Serial
Channel
Programmable I/O
RC32333
32-bit, 50MHz PCI
Local
Memory
I/O Bus
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