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參數(shù)資料
| 型號(hào)： | IDT72T6360L7-5BBI |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 51/51頁 |
| 文件大小： | 0K |
| 描述： | IC FLOW-CTRL 48BIT 7-5NS 324-BGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 連續(xù)流量控制 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 324-BGA |
| 供應(yīng)商設(shè)備封裝： | 324-PBGA（19x19） |
| 包裝： | 托盤 |
| 其它名稱： | 72T6360L7-5BBI |
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9
IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE
x9, x18, x36 BIT WIDE CONFIGURATION
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
FEBRUARY 10, 2009
CONTROL AND FEATURE INTERFACE (Continued)
JSEL(1)
P11
JTAGSelect
INPUT
This pin selects whether the JTAG pins will be used for serial programming. If JSEL is
3.3V or
HIGH, the JTAG pins will only be used for JTAG boundary-scan function. If JSEL is LOW,
2.5V LVTTL the JTAG function is disabled and the JTAG pins will be used for serial programming of the
PAE/PAFoffsetregisters.
MIC[2:0](1) MIC2-U10 Memory
INPUT
These signals enable the EDC feature of the device. See Table 8, MIC[2:0] Configurations
MIC1-R10 Configuration
3.3V or
fordetails.
MIC0-P10
2.5V LVTTL
MCLK
H1
Master Clock
INPUT
33MHz reference clock used to generate CK and
CK for external memory interface.
3.3V or
2.5V LVTTL
MRS
V5
Master Reset
INPUT
Master reset initializes the read and write pointers to zero and sets the output register to all
3.3V or
zeros. All initialized settings for the device will be configured during master reset.
2.5V LVTTL
MSPEED(1)
T8
Memory Speed
INPUT
This input select the speed of the external memory interfacing the sequential flow-control
3.3V or
device. A LOW selects 133MHz, and HIGH selects 166MHz.
2.5V LVTTL
MTYPE(1)
MTYPE1-U8
Memory Type
INPUT
These inputs select which type of external memory is interfacing the sequential flow-control
[1:0]
MTYPE0-R8
[1:0]
3.3V or
device. See Table 14 for the list of selectable memories.
2.5V LVTTL
PRS
U6
PartialReset
INPUT
Partial reset initializes the read and write pointers to zero and sets the output registers to all
3.3V or
zeros. All existing configurations in the sequential flow-control device will not be affected.
2.5V LVTTL This includes the IDT Standard or FWFT mode timing, programmable flag settings, and
bus width and data rate mode.
TCK/
U11
JTAG Clock/
INPUT
Thisisadualfunctionpin.WhentheJSELpinisHIGH,thisistheclockinputforJTAGboundary-
SCLK
Serial Clock
3.3V or
scan function. One of four terminals required by IEEE Standard 1149.1-1990. Test operations
2.5V LVTTL of the device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge
of TCK and outputs change on the falling edge of TCK.
When the JSEL pin is LOW, this is the serial clock input for writing and reading the
PAE/PAF
offset registers. On the rising edge of every SCLK when
SWEN is LOW, one bit of data from
theSIpinisshiftedintothe
PAEandPAFoffsetregisters.OntherisingedgeofeachSCLKwhen
SRENisLOW,onebitofdatafromtheSOpinisshiftedoutofthe
PAEandPAFoffsetregisters.
If the JTAG or serial programming is not used this signal needs to be tied to GND.
TDI/SI
R11
JTAG Test Data
INPUT
This is a dual function pin. When the JSEL pin is HIGH, this is the JTAG test data input pin. One
Input/ Serial Input
3.3V or
of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
2.5V LVTTL operation, test data serially loaded via the TDI on the rising edge of TCK to the Instruction
Register, ID Register and Bypass Register.
When the JSEL pin is LOW, this is the serial input pin for the
PAE/PAF offset registers. An
internal pull-up resistor forces TDI/SI HIGH if left unconnected.
TDO/SO
P12
JTAG Test Data
OUTPUT
This is a dual function pin. When the JSEL pin is HIGH, this is the JTAG test data output pin.
Output/SerialOutput
3.3V or
One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary
2.5V LVTTL scan operation, test data serially loaded output via the TDO on the falling edge of TCK from
eithertheInstructionRegister,IDRegisterandBypassRegister.Thisoutputishigh-impedance
except when shifting, while in SHIFT-DR and SHIFT-IR controller states.
When the JSEL pin is LOW, this is the serial data output pin for the
PAE/PAF offset registers.
TMS
T10
JTAG Mode Select
INPUT
TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS
3.3V or
directsthedevicethroughitsTAPcontrollerstates.Aninternalpull-upresistorforcesTMSHIGH
2.5V LVTTL ifleftunconnected.
PIN DESCRIPTIONS (Continued)
Symbol
Pin No.
Name
I/O TYPE
Description
Location
Please see next page for Power & Ground pins and Pin Number Location Table.
NOTE: 1. These pins should not change after master reset.
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