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參數(shù)資料
| 型號： | IDT72T6360L7-5BBI |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 34/51頁 |
| 文件大小： | 0K |
| 描述： | IC FLOW-CTRL 48BIT 7-5NS 324-BGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 連續(xù)流量控制 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 324-BGA |
| 供應(yīng)商設(shè)備封裝： | 324-PBGA（19x19） |
| 包裝： | 托盤 |
| 其它名稱： | 72T6360L7-5BBI |
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IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE
x9, x18, x36 BIT WIDE CONFIGURATION
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
FEBRUARY 10, 2009
DESCRIPTION
The IDT72T6360 sequential flow-control device is a device incorporating
a seamless connection to external DDR SDRAM for significant storage
capacity supporting high-speed applications. Both read and write ports of the
sequential flow-control can operate independently at up to 166MHz. There
is a user selectable correction feature that will correct any erroneous single
data bit when reading from the SDRAM.
The independent read and write ports each has associated read and write
clocks, enables, and chip selects. Both ports can operate either synchro-
nously or asynchronously. Other features include bus-matching, program-
mablestatusflagswithselectablesynchronous/asynchronoustimingmodes,
IDT Standard or FWFT mode timing, and JTAG boundary scan functionality.
Thebus-matchingfeaturewillallowtheinputsandoutputstobeconfigured
to x36, x18, or x9 bus width. There are four default offset values available
for the programmable flags (
PAE/PAF), as well as the option of serially
programming the offsets to a specific value.
The device package is 19mm x 19mm 324-pin PBGA. It operates at a 2.5V
core voltage with selectable 2.5V or 3.3V I/Os. The I/O interface to the SDRAM
will be 2.5V SSTL_2 only and not 3.3V tolerant. Both industrial and commercial
temperature ranges will be offered.
The sequential flow-control device controls individual DDR SDRAM of either
128Mb or 256Mb. The device will support industry standard DDR specification
memories (note DDR II is not supported), which include vendors such as
Samsung, Micron, and Infineon. The data bus connected to the DDR SDRAM
can be 16-bit, 32-bit, or 64-bits wide. The sequential flow-control device can
independently control up to four separate external memories for a maximum of
density of 1Gb (128MB). Depth expansion mode is available for applications
that require more than 1Gb of storage memory.
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| IDT72T6480L10BB | 功能描述:IC FLOW-CTRL 48BIT 10NS 324-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72T6480L10BBI | 功能描述:IC FLOW-CTRL 48BIT 10NS 324-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72T6480L7-5BB | 功能描述:IC FLOW-CTRL 48BIT 7-5NS 324-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72T6480L7-5BBG | 功能描述:IC FLOW-CTRL 48BIT 7-5NS 324-BGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72T72105L10BB | 功能描述:IC FIFO 65536X72 10NS 324-BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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