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參數資料
| 型號： | IDT72T6360L7-5BBI |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數： | 3/51頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FLOW-CTRL 48BIT 7-5NS 324-BGA |
| 標準包裝： | 1 |
| 類型： | 連續(xù)流量控制 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 324-BGA |
| 供應商設備封裝： | 324-PBGA（19x19） |
| 包裝： | 托盤 |
| 其它名稱： | 72T6360L7-5BBI |
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11
IDT72T6360 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE
x9, x18, x36 BIT WIDE CONFIGURATION
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
FEBRUARY 10, 2009
DETAILED DESCRIPTIONS
SEQUENTIAL FLOW-CONTROL STRUCTURE
The IDT sequential flow-control (SFC) device is comprised of three inter-
faces: input port, output port, and memory interface. The input and output port
can operate independently of each other with selectable bus widths of x9, x18,
or x36 bits wide. The third interface, or memory interface, is connected directly
to an external memory, which can be used to offload data entering the SFC
device.
WRITING AND READING FROM THE SEQUENTIAL FLOW-CONTROL
DEVICE
WritingintotheSFCdeviceisaccomplishedbysettingthewriteenablesignal
(
WEN)andwritechipselect(WCS)lowwithafreerunningwriteclock(WCLK).
Data will be written on the rising edge of every WCLK into the Quad-Port (QP)
cacheoftheSFCdevice. Theinternalstatemachineofthedevicewilldetermine
whether to send the data to the DDR SDRAM or send it directly through to the
outputbus,dependingonwhenthedataistobeaccessed. Thisprovides“data
coherency” and minimizes the path that the data has to travel.
Reading from the SFC device is accomplished by setting the read enable
signal (
REN) and read chip select (RCS) low with a free running read clock
(RCLK). Data will be sent to the output bus on the rising edge of every RCLK.
This data will be accessed either from the QP cache or the external DDR
SDRAM.
EXTERNAL MEMORY SELECTION
The DDR SDRAM interface of the SFC device can support DDR SDRAM
with standard DDR I specifications. The SFC device can support any external
memorywithinthefollowingcharacteristics:
Bus width: 16-bit or 32-bit wide
Speed: 133MHz or 166MHz
Density: 128Mb or 256Mb
Table1liststheDDRSDRAMminimumspecificationsthatarerequiredtomeet
the sequential flow-control device requirements. Table 2 lists the memory
vendors and associated part numbers of DDR SDRAMs that have been
validated by IDT to meet the requirements for the DDR SDRAM interface.
DDR SDRAM Minimum Specifications
Symbol
Parameter
16-bit DDR
32-bit DDR
Units
SDRAM
tCK
CL = 2.5
Clock cycle time
6
n/a
ns
CL = 3.0
n/a
6
tRFC
Auto refresh command period
75
63
ns
tRCD
Active to read/write delay
20
n/a
ns
tRP
Precharge comman period
20
18
ns
tWR
Write recovery time
15
1.5
ns
tRCDRD
Active to read delay
n/a
18
ns
tRCDWR
Active to write delay
n/a
9
ns
TABLE 1 – DDR SDRAM MINIMUM SPECIFICATIONS
Density
Bus Width
Vendor
Part#
128Mb
32
Samsung
K4D263238"X"-GC45
256Mb
16
Samsung
K4H561638"X"-TCLB3
K4H561638"X"-GCLB3
256Mb
16
Micron
MT46V16M16TG-6T
MT46V16M16TG-75
256Mb
16
Infineon
HYB25D256160BTL-6
HYB25D256160BTL-7
256Mb
32
Samsung
K4D553238"X"-JC50
TABLE 2 – SUPPORTED MEMORY VENDORS
NOTES
:
1. The part numbers listed above include packages that are recommended and validated by IDT.
Other packages (such as lead free PCB, FBGA, etc.) may also be used but have not been
validated by IDT.
2. The letter "X" for Samsung memory part numbers denotes the latest die revision for that particular
device. Check with Samsung for the latest updated part number.
NOTE
:
1. These are the minimum specifications that the DDR SDRAM must meet.
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