參數(shù)資料
型號(hào)： IBMN364164CT3C-75A
英文描述： x16 SDRAM
中文描述： x16內(nèi)存
文件頁數(shù)： 27/71頁
文件大小： 1251K
代理商： IBMN364164CT3C-75A
IBMN364164
IBMN364404
IBMN364804
64Mb Synchronous DRAM - Die Revision C
19L3265.E35856B
1/01
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 27 of 71
Automatic Refresh Command (CAS before RAS Refresh)
When CS, RAS, and CAS are held low with CKE and WE high at the rising edge of the clock, the chip enters
the Automatic Refresh mode (CBR). All banks of the SDRAM must be precharged and idle for a minimum of
the Precharge time (t
RP
) before the Auto Refresh Command (CBR) can be applied. An address counter,
internal to the device provides the address during the refresh cycle. No control of the external address pins is
required once this cycle has started.
When the refresh cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay
between the Auto Refresh Command (CBR) and the next Activate Command or subsequent Auto Refresh
Command must be greater than or equal to the RAS cycle time (t
RC
).
Self Refresh Command
The SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh Command
is defined by having CS, RAS, CAS, and CKE held low with WE high at the rising edge of the clock. All banks
must be idle prior to issuing the Self Refresh Command. Once the command is registered, CKE must be held
low to keep the device in Self Refresh mode. When the SDRAM has entered Self Refresh mode all of the
external control signals, except CKE, are disabled. The clock is internally disabled during Self Refresh Oper-
ation to save power. The user may halt the external clock while the device is in Self Refresh mode, however,
the clock must be restarted before the device can exit Self Refresh operation. Once the clock is cycling, the
device will exit Self Refresh operation after CKE is returned high. A minimum delay time is required when the
device exits Self Refresh Operation and before the next command can be issued. This delay is equal to the
RAS cycle time (t
RC
) plus the Self Refresh exit time (t
SREX
).
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