參數(shù)資料
型號(hào)： IBMN364164CT3C-75A
英文描述： x16 SDRAM
中文描述： x16內(nèi)存
文件頁(yè)數(shù)： 15/71頁(yè)
文件大?。?/td> 1251K
代理商： IBMN364164CT3C-75A
IBMN364164
IBMN364404
IBMN364804
64Mb Synchronous DRAM - Die Revision C
19L3265.E35856B
1/01
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 15 of 71
Burst Write Command
The Burst Write command is initiated by having CS, CAS, and WE low while holding RAS high at the rising
edge of the clock. The address inputs determine the starting column address. There is no CAS latency
required for burst write cycles. Data for the first burst write cycle must be applied on the DQ pins on the same
clock cycle that the Write Command is issued. The remaining data inputs must be supplied on each subse-
quent rising clock edge until the burst length is completed. When the burst has finished, any additional data
supplied to the DQ pins will be ignored.
Write Interrupted by a Write
A burst write may be interrupted before completion of the burst by another Write Command. When the previ-
ous burst is interrupted, the remaining addresses are overridden by the new address and data will be written
into the device until the programmed burst length is satisfied.
Burst Write Operation
Write Interrupted by a Write
COMMAND
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
DQs
DIN A
0
DIN A
1
DIN A
2
DIN A
3
NOP
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
Extra data is masked.
The first data element and the Write
are registered on the same clock edge.
(
Burst Length = 4, CAS latency = 2, 3)
: “H” or “L”
COMMAND
NOP
WRITE A
WRITE B
NOP
NOP
NOP
NOP
NOP
DQs
DIN A
0
DIN B
0
DIN B
1
DIN B
2
NOP
DIN B
3
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
1 Clk Interval
(Burst Length = 4, CAS latency = 2, 3)
相關(guān)PDF資料
PDF描述
IBMN364404CT3C-260 x4 SDRAM
IBMN364404CT3C-360 x4 SDRAM
IBMN364404CT3C-75A x4 SDRAM
IBMN364804CT3C-260 x8 SDRAM
IBMN364804CT3C-360 x8 SDRAM
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