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參數(shù)資料
| 型號(hào)： | HY5R288HC |
| 英文描述： | -|2.5V|8K|40|Direct RDRAM - 288M |
| 中文描述： | - |為2.5V | 8K的| 40 |直接RDRAM的- 288M |
| 文件頁數(shù)： | 47/64頁 |
| 文件大?。?/td> | 4542K |
| 代理商： | HY5R288HC |
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Rev.0.9 / Dec.2000
47
Direct RDRAM
256/288-Mbit (512Kx16/18x32s) Preliminary
Timing Conditions.
Table 18: Timing Conditions
Symbol
Parameter
Min
Max
Unit
Figure(s)
t
DCW
Domain crossing window
-0.1
0.1
t
CYCLE
Figure 60:
t
DR
, t
DF
DQA/DQB/ROW/COL input rise/fall times (20% to 80%)
Use the minimum value of these parameters during testing.
0.2
0.65
ns
Figure 55:
t
S
, t
H
DQA/DQB/ROW/COL-to-CFM setup/hold
@ t
CYCLE
=2.50ns/2.81ns/3.33ns
0.200
b
/0.240
b,c
/0.275
b,d
-
ns
Figure 55:
t
DR1,
t
DF1
SIO0, SIO1 input rise and fall times
-
5.0
ns
Figure 57:
t
DR2,
t
DF2
CMD, SCK input rise and fall times
-
2.0
ns
Figure 57:
t
CYCLE1
SCK cycle time - Serial control register transactions
1000
-
ns
Figure 57:
SCK cycle time - Power transitions
10
-
ns
Figure 57:
t
S1
CMD setup time to SCK rising or falling edge
e
1.25
-
ns
Figure 57:
t
H1
CMD hold time to SCK rising or falling edge
e
1
-
ns
Figure 57:
t
CH1
, t
CL1
SCK high and low times
4.25
-
ns
Figure 57:
t
S2
SIO0 setup time to SCK falling edge
40
-
ns
Figure 57:
t
H2
SIO0 hold time to SCK falling edge
40
-
ns
Figure 57:
t
S3
PDEV setup time on DQA5..0 to SCK rising edge.
0
-
ns
Figure 48:,
Figure 57:
t
H3
PDEV hold time on DQA5..0 to SCK rising edge.
5.5
-
ns
t
S4
ROW2..0, COL4..0 setup time for quiet window
-1
-
t
CYCLE
Figure 48:
t
CYCLE
CTM and CFM cycle times (-600)
3.33
3.83
ns
Figure 54:
CTM and CFM cycle times (-711)
2.80
3.83
ns
Figure 54:
CTM and CFM cycle times (-800)
2.50
3.83
ns
Figure 54:
t
CR
, t
CF
CTM and CFM input rise and fall times
0.2
0.5
ns
Figure 54:
t
CH
, t
CL
CTM and CFM high and low times
40%
60%
t
CYCLE
Figure 54:
t
TR
CTM-CFM differential (MSE/MS=0/0)
CTM-CFM differential (MSE/MS=1/1)
a
0.0
0.9
1.0
1.0
t
CYCLE
Figure 42:
Figure 54:
t
H4
ROW2..0, COL4..0 hold time for quiet window
f
5
-
t
CYCLE
Figure 48:
t
NPQ
Quiet on ROW/COL bits during NAP/PDN entry
4
-
t
CYCLE
Figure 47:
t
READTOCC
Offset between read data and CC packets (same device)
12
-
t
CYCLE
Figure 52:
t
CCSAMTOREAD
Offset between CC packet and read data (same device)
8
-
t
CYCLE
Figure 52:
t
CE
CTM/CFM stable before NAP/PDN exit
2
-
t
CYCLE
Figure 48:
t
CD
CTM/CFM stable after NAP/PDN entry
100
-
t
CYCLE
Figure 47:
t
FRM
ROW packet to COL packet ATTN framing delay
7
-
t
CYCLE
Figure 46:
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