參數(shù)資料
型號(hào)： HY5R288HC
英文描述： -|2.5V|8K|40|Direct RDRAM - 288M
中文描述： - |為2.5V | 8K的| 40 |直接RDRAM的- 288M
文件頁(yè)數(shù)： 37/64頁(yè)
文件大?。?/td> 4542K
代理商： HY5R288HC
Rev.0.9 / Dec.2000
37
Direct RDRAM
256/288-Mbit (512Kx16/18x32s) Preliminary
Figure 43: TEST Register
Figure 42: SKIP Register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Read/write register (except AS field)
Reset value is zero (SIO Reset).
AS-Autoskip. Read-only value determined by auto
skip circuit and stored when SETF serial command is
RDRAM during initialization. In figure58, AS=1
corresponds to the early Q(a1) packet and AS=0 to the
tCYCLE later for the four uncertain cases. MSE-
Manual skip enable (0=auto, 1=manual). MS-Manual
skip (MS must be 1 when MSE=1). During initializa-
tion, the RDRAMs at the furthest point in the fifth read
domain may have selected the AS=0 value, placing
them at the closest point in a sixth read domain. Setting
the MSE/MS fields to 1/1 overrides the autoskip value
and returns them to the furthest point of the fifth read
domain.
Control Register: SKIP
Address: 04b
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AS MSE AS
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Read/write registers.
Reset value of TEST78,79 is zero ( SIO Reset).
Do not read or write TEST78,79 after SIO reset.
TEST77 must be written with zero after SIO reset.
These registers must only be used for testing purposes
except prior to the SETR/CLRR sequence when
TEST78 is written with a temporary value.After
SETR/CLRR it is rewritten to 0000
16
.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Control Register: TEST77
Address: 04d
16
Address: 04e
16
Address: 04f
16
Control Register: TEST78
Control Register: TEST79
Figure 44: TCYCLE Register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Read/write register.
Reset value is undefined
TCYCLE13..0 - Specifies the value of the t
CYCLE
datasheet parameter in 64ps units. For the t
CYCLE,MIN
of 2.5ns (2500ps), this field should be written with the
value “00027
16
” (3964ps).
Control Register: TCYCLE
Address: 04c
16
0
0
TCYCLE13..TCYCLE0
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