參數(shù)資料
型號(hào)： HY5DU561622FTP-4I
廠商： HYNIX SEMICONDUCTOR INC
元件分類(lèi)： DRAM
英文描述： 16M X 16 DDR DRAM, 0.7 ns, PDSO66
封裝： 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66
文件頁(yè)數(shù)： 18/28頁(yè)
文件大?。?/td> 179K
代理商： HY5DU561622FTP-4I
Rev. 1.1 / Mar. 2008
25
1HY5DU561622FTP-5I
HY5DU561622FTP-4I
Note :
1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2. Data sampled at the rising edges of the clock : A0~A12, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.
3. Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM.
4. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
5. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this
value can be greater than the minimum specification limits for tCL and tCH).
6. tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS consists of
tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects, and p-channel to
n-channel variation of the output drivers.
7. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times.
Signal transitions through the DC region must be monotonic.
Data-In Hold Time to DQS-In (DQ & DM)
tDH
0.4
-
0.4
-
ns
3
Read DQS Preamble Time
tRPRE
0.9
1.1
0.9
1.1
CK
Read DQS Postamble Time
tRPST
0.4
0.6
0.4
0.6
CK
Write DQS Preamble Setup Time
tWPRES
0-
ns
Write DQS Preamble Hold Time
tWPREH
1.5
-
1.5
-
ns
Write DQS Postamble Time
tWPST
0.4
0.6
0.4
0.6
CK
Mode Register Set Delay
tMRD
2-
CK
Exit Self Refresh to Any Execute Command
tXSC
200
-
200
-
CK
4
Power Down Exit Time
Except Read
Command
tPDEX
1tCK
+ tIS
-
1tCK
+ tIS
-CK
Read Command
tPDEX_RD
2tCK
+ tIS
-
2tCK
+ tIS
-CK
Average Periodic Refresh Interval
tREFI
-7.8
us
Parameter
Symbol
4
5
Unit
Note
Min
Max
Min
Max
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HY5DU561622FTP-5 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M(16Mx16) DDR SDRAM
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HY5DU561622FTP-D43I 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256Mb DDR SDRAM
HY5DU561622FTP-D5 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256Mb DDR SDRAM
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