參數(shù)資料
型號: HV7131D-COF
廠商: HYNIX SEMICONDUCTOR INC
元件分類: 模擬信號調(diào)理
英文描述: CMOS IMAGE SENSOR With 8-bit ADC
中文描述: SPECIALTY ANALOG CIRCUIT, DSS24
封裝: COF-24
文件頁數(shù): 37/61頁
文件大小: 2621K
代理商: HV7131D-COF
HV7131GP
2004/10/29 V2.4 37
AE Anti-Banding Step High
1
1
1
0
1
0
0
0
AE Anti-Banding Step Low [AEANTL : 6ch : 48h]
7
6
5
4
3
2
1
0
AE Anti-Banding Step Low
0
1
0
0
1
0
0
0
AE Anti-Banding Step specifies integration time unit value that AE uses when Anti-Banding is enabled.
Anti-Banding Step value is resolved by the following equation.
Anti-Banding Step Value = Sensor Operation Frequency (SCF) / (2x power line frequency)
The default value is set with SCF 12.5Mhz, 50Hz power line, that is,
Anti-Banding Step Value = 12.5Mhz / (2 x 50) = 125000d = 1e848h
AE Integration Time Limit High [AELMH : 6dh : 17h]
7
6
5
4
3
2
1
0
AE Integration Time Limit High
0
0
0
1
0
1
1
1
AE Integration Time Limit Middle [AELMM : 6eh : d7h]
7
6
5
4
3
2
1
0
AE Integration Time Limit Middle
1
1
0
1
0
1
1
1
AE Integration Time Limit Low [AELML : 6fh : 84h]
7
6
5
4
3
2
1
0
AE Integration Time Limit Low
1
0
0
0
0
1
0
0
These three registers define the maximum integration time value that is allowed to sensor operation. It
is desirable to set the value to multiples of AE Anti-Banding Step to easily operate with Anti-banding
mode enabled. The default value is set to 1/8sec with SCF set to 25Mhz
12.5Mhz / 8 = 1,562,500 = 17d784
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