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參數(shù)資料
| 型號： | HM624100H |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Dual J-K Negative-Edge-Triggered Flip-Flops With Preset And Clear 16-CFP -55 to 125 |
| 中文描述： | 4分高速SRAM（1 - Mword × 4位） |
| 文件頁數(shù)： | 3/13頁 |
| 文件大?。?/td> | 74K |
| 代理商： | HM624100H |
HM624100H Series
3
Pin Description
Pin name
Function
A0 to A19
Address input
I/O1 to I/O4
CS
OE
WE
Data input/output
Chip select
Output enable
Write enable
V
CC
V
SS
NC
Power supply
Ground
No connection
Block Diagram
I/O1
.
.
.
I/O4
WE
CS
Input
data
control
Column I/O
Column decoder
Memory matrix
256 rows
×
16 columns
×
256 blocks
×
4 bit
(4,194,304 bits)
Row
decoder
OE
CS
CS
V
CC
V
SS
CS
A1
A17
A7
A11
A16
A2
A6
A5
(MSB)
A10 A8 A9 A19 A12 A13 A14 A0 A18 A15 A3 A4
(LSB)
(MSB)
(LSB)
Internal
voltage
generater
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HM624100HLJP-10 | 4M High Speed SRAM (1-Mword x 4-bit) |
| HM624100HLJP-12 | 4M High Speed SRAM (1-Mword x 4-bit) |
| HM624100HLJP-15 | 4M High Speed SRAM (1-Mword x 4-bit) |
| HM624256A | 262144-word ×4-bit High Speed CMOS Static RAM(262144字 ×4位高速CMOS SRAM) |
| HM6264AFP-10 | Dual J-K Negative-Edge-Triggered Flip-Flops With Preset And Clear 16-CDIP -55 to 125 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM624100HC | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:4M High Speed SRAM (1-Mword x 4-bit) |
| HM624100HCJP-10 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:4M High Speed SRAM (1-Mword x 4-bit) |
| HM624100HCJP-12 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SRAM: Notes on Usage Technical Update/Device |
| HM624100HCLJP-10 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:4M High Speed SRAM (1-Mword x 4-bit) |
| HM624100HCLJP-12 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SRAM: Notes on Usage Technical Update/Device |
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