參數(shù)資料
型號: HM624100H
廠商: Hitachi,Ltd.
英文描述: Dual J-K Negative-Edge-Triggered Flip-Flops With Preset And Clear 16-CFP -55 to 125
中文描述: 4分高速SRAM(1 - Mword × 4位)
文件頁數(shù): 11/13頁
文件大?。?/td> 74K
代理商: HM624100H
HM624100H Series
11
Low V
CC
Data Retention Characteristics
(Ta = 0 to +70
°
C)
This characteristics is guaranteed only for L-version.
Parameter
Symbol
Min
Typ*
1
Max
Unit
Test conditions
V
CS
V
CC
– 0.2 V
(1) 0 V
Vin
0.2 V or
(2) V
CC
Vin
V
CC
– 0.2 V
V
= 3 V, V
CC
CS
V
CC
– 0.2 V
(1) 0 V
Vin
0.2 V or
(2) V
CC
Vin
V
CC
– 0.2 V
See retention waveform
V
CC
for data retention
V
DR
2.0
V
Data retention current
I
CCDR
50
800
μ
A
Chip deselect to data
retention time
t
CDR
0
ns
Operation recovery time
Note: 1. Typical values are at V
CC
= 3.0 V, Ta = +25C, and not guaranteed.
t
R
5
ms
Low V
CC
Data Retention Timing Waveform
V
CC
3.0 V
2.2 V
0 V
CS
t
CDR
t
R
V
CC
CS
V
CC
– 0.2 V
V
DR
Data retention mode
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