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參數(shù)資料
| 型號(hào)： | HDMP-3001K |
| 英文描述： | Evaluation Board for Multi-Protocol IC (MPIC) Ethernet Over SONET/SDH (EOS) Mapper |
| 中文描述： | 評(píng)估板多協(xié)議芯片（守約）SONET的以太網(wǎng)/ SDH的（EOS）上映射 |
| 文件頁(yè)數(shù)： | 2/12頁(yè) |
| 文件大?。?/td> | 177K |
| 代理商： | HDMP-3001K |
2
The design of the HDMP-0421
allows for placement of the CDR
at one of two locations with
respect to a hard disk slot. For
example, if the BYPASS[0]– pin
is HIGH and hard disk slot A is
connected to PBC cell 1, the CDR
function will be performed before
entering the hard disk at slot A
Figure 2. Timing Waveforms.
Figure 1. Block Diagram of HDMP-0421.
(Figure 4). To achieve a CDR
function after slot A, the
BYPASS[1]– pin must be HIGH
and hard disk slot A must be
connected to PBC cell 0
(Figure 5). Table 2 shows both
possible connections. In both
cases, a Signal Detect (SD) pin
shows the status of the signal at
the incoming cable. The
recommended method of setting
the BYPASS[i]– pins HIGH is to
drive them with a high-
impedence signal. Internal pull-
up resistors will force the
BYPASS[I]– pins to V
CC
.
(1) FM_NODE[0]
(2) FM_NODE[4]
(1) TO_NODE[0]
(2) TO_NODE[0]
t
delav1.2
LOSDET
TO_NODE[1]
FM_NODE[1]
BYPASS[1]–
SD[1]
IOSDET
SD[0]
CDR
REFCLK
CEXT
1
0
BYPASS[0]–
1
0
TO_NODE[0]
FM_NODE[0]
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