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參數(shù)資料
| 型號(hào)： | HDMP-2689 |
| 英文描述： | Quad 2.125/1.0625 GBd Fibre Channel General Purpose SerDes |
| 中文描述： | 四2.125/1.0625 GBd光纖通道通用的SerDes |
| 文件頁數(shù)： | 11/28頁 |
| 文件大?。?/td> | 356K |
| 代理商： | HDMP-2689 |
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11
HDMP-2689 Receiver Section Timing Characteristics,
T
C
= 0
°
C to T
C
= 85
°
C, V
DDQ
= 2.3 to 2.7 V, V
DD
= 1.7 to 1.9 V, V
DDA
= 1.7 to 1.9 V
Symbol
Parameters
Units
Min
Typ
Max
PWreset
Width of reset pulse
ns
100
f lockRX
The time that the RX PLL takes to frequency lock to the data after reset
μ
s
500
B_sync_lock
Bit Sync time after f lockRX
bits
2500
B_sync_rate
Bit Sync time after rate switch
μ
s
100
1G
RX
S
[1]
Setup time: the time before the clock edge that the data will be stable
ps
2700
RX
H[1]
Hold time; the time after the clock edge until which the data will remain stable
ps
1500
t_RXlat_buffer
Receiver latency; the timing between the leading edge of the first received serial
bit of a parallel data word and the leading edge of the corresponding parallel output
word in buffer mode
ns
bits
50
53
t_RXlat_codec
Receiver latency; the timing between the leading edge of the first received serial
bit of a parallel data word and the leading edge of the corresponding parallel output
word in codec mode
ns
bits
60
64
2G
RX
S
[1]
Setup time: the time before the clock edge that the data will be stable
ps
1200
RX
H[1]
Hold time; the time after the clock edge until which the data will remain stable
ps
1400
t_RXlat_buffer
Receiver latency; the timing between the leading edge of the first received serial
bit of a parallel data word and the leading edge of the corresponding parallel output
word in buffer mode
ns
bits
30
64
t_RXlat_codec
Receiver latency; the timing between the leading edge of the first received serial
bit of a parallel data word and the leading edge of the corresponding parallel output
word in codec mode
ns
bits
35
75
Notes:
1. Tested under load conditions described in Figure 12, with V
IH
= V
REF
+ 0.18 and V
IL
= V
REF
–
0.18.
SSTL_2
OUTPUT DRIVER
Z
0
= 50
DELAY = 1.0 - 2.0ns
C
LOAD
= 4 pF
50
VTERM (VDDQ/2)
Note:
Register 23 set to 0x1218.
power supplies and RFCN/
RFCP have stabilized
RSTN
20
μ
s
100 ns
PW reset
500
μ
s
f
lockRX
program MDIO
Figure 12. SSTL_2 Output Test Conditions.
Figure 13. Externally Applied Reset (not to scale).
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