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參數(shù)資料
| 型號： | HDMP-1526 |
| 英文描述： | Transistor Diode Kit;Contents Of Kit:Transistor/Diode Kit |
| 中文描述： | 光纖通道收發(fā)器芯片 |
| 文件頁數(shù)： | 2/14頁 |
| 文件大?。?/td> | 229K |
| 代理商： | HDMP-1526 |
683
HDMP-1526
PROTOCOL DEVICE
SERIAL DATA OUT
RECEIVER SECTION
PLL
TRANSMITTER SECTION
BYTSYNC
-LCKREF
ENBYTSYNC
REFCLK
SERIAL DATA IN
PLL
Figure 1. Typical Application Using the HDMP-1526.
± DOUT
TX
PLL/CLOCK
GENERATOR
REFCLK
-LCKREF
RXCAP0
RXCAP1
RBC0
RBC1
± DIN
BYTSYNC
ENBYTSYNC
O
D
INTERNAL
Tx CLOCKS
I
L
DATA BYTE
RX[0-9]
TXCAP1
TXCAP0
DATA BYTE
TX[0-9]
INTERNAL
Rx CLOCKS
LOOPEN
INTERNAL
LOOPBACK
OUTPUT
SELECT
FRAME
MUX
RX
PLL/CLOCK
RECOVERY
INPUT
SELECT
FRAME
DEMUX
AND
BYTE SYNC
INPUT
SAMPLER
Figure 2. HDMP-1526 Transceiver Block Diagram.
HDMP-1526 Block Diagram
The HDMP-1526 was designed to
transmit and receive 10-bit wide
parallel data over a single high-
speed line, as specified for the FC-0
layer of the Fibre Channel standard.
The parallel data applied to the
transmitter is expected to be
encoded per the Fibre Channel
specification, which uses an 8B/10B
encoding scheme with special
reserve characters for link
management purposes. In order to
accomplish this task, the HDMP-
1526 incorporates the following:
TTL Parallel I/Os
High-Speed Phase Lock Loops
Clock Generation/Recovery
Circuitry
Parallel-to-Serial Converter
High-Speed Serial Clock-and-Data
Recovery Circuitry
Comma Character Recognition
Circuitry
Byte Alignment Circuitry
Serial-to-Parallel Converter
INPUT LATCH
The transmitter accepts 10-bit wide
TTL parallel data at inputs TX[0..9].
The user-provided reference clock
signal, REFCLK, is also used as the
transmit byte clock. The TX[0..9]
and REFCLK signals must be
properly aligned, as shown in
Figure 3.
TX PLL/CLOCK GENERATOR
The transmitter Phase Lock Loop
and Clock Generator (TX PLL/
CLOCK GENERATOR) block is
responsible for generating all
internal clocks needed by the
transmitter section to perform its
functions. These clocks are based on
the supplied reference byte clock
(REFCLK). REFCLK is used as both
the frequency reference clock for
the PLL and the transmit byte clock
for the incoming data latches. It is
expected to be 106.25 MHz and
properly aligned to the incoming
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| HDMP-1546A | Fibre Channel Transceiver Chip(光纖通道收發(fā)器芯片) |
| HDMP-1536A | Fibre Channel Transceiver Chip(光纖通道收發(fā)器芯片) |
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| HDMP-1536 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transceiver Chip |
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| HDMP-1546 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transceiver Chip |
| HDMP-1546A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:IC-TRANSCEIVER |
| HDMP-1636 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Gigabit Ethernet Transceiver Chip |
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