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參數(shù)資料
| 型號： | HDMP-1546A |
| 英文描述： | Fibre Channel Transceiver Chip(光纖通道收發(fā)器芯片) |
| 中文描述： | 光纖通道收發(fā)器芯片（光纖通道收發(fā)器芯片） |
| 文件頁數(shù)： | 1/16頁 |
| 文件大?。?/td> | 246K |
| 代理商： | HDMP-1546A |
Fibre Channel Transceiver Chip
Technical Data
HDMP-1536A Transceiver
HDMP-1546A Transceiver
Features
ANSI X3.230-1994 Fibre
Channel Compatible (FC-0)
Supports Full Speed
(1062.5 MBd) Fibre Channel
Compatible with “Fibre
Channel 10-Bit Interface”
Specification
Low Power Consumption,
630 mW
Transmitter and Receiver
Functions Incorporated onto
a Single IC
Auto Frequency Lock
Small Package Profile
HDMP-1536A, 10x10 mm
QFP
HDMP-1546A, 14x14 mm
QFP
10-Bit Wide Parallel TTL
Compatible I/Os
Single +3.3 V Power Supply
5 Volt Tolerant I/Os
2 kV ESD Protection on AllPins
Applications
1062.5 MBd Fibre Channel
Interface
FC Interface for Disk Drives
and Arrays
Mass Storage System I/O
Channel
Work Station/Server I/O
Channel
High Speed Proprietary
Interface
High Speed Backplane
Interface
Description
The HDMP-1536/46A transceiver
is a single silicon bipolar
integrated circuit packaged in a
plastic QFP package. It provides
a low-cost, low-power physical
layer solution for 1062.5 MBd
Fibre Channel or proprietary link
interfaces. It provides complete
FC-0 functionality for copper
transmission, incorporating both
the Fibre Channel FC-0 transmit
and receive functions into a
single device.
This chip is used to build a high-
speed interface (as shown in
Figure 1) while minimizing board
space, power, and cost. It is
compatible with both the ANSI
X3.230-1994/AM 1 - 1996
document and the “Fibre Channel
10-bit Interface” specification.
The transmitter section accepts
10-bit wide parallel TTL data and
multiplexes this data into a high-
speed serial data stream. The
parallel data is expected to be
8B/10B encoded data, or
equivalent. This parallel data is
latched into the input register of
the transmitter section on the
rising edge of the 106.25 MHz
reference clock (used as the
transmit byte clock).
The transmitter section’s PLL
locks to this user supplied 106.25
MHz byte clock. This clock is
then multiplied by 10, to generate
the 1062.5 MHz serial signal
clock used to generate the high-
speed output. The high-speed
outputs are capable of interfacing
directly to copper cables for
electrical transmission or to a
separate fiber-optic module for
optical transmission.
The receiver section accepts a
serial electrical data stream at
1062.5 MBd and recovers the
original 10-bit wide parallel data.
The receiver PLL locks onto the
incoming serial signal and
相關PDF資料 |
PDF描述 |
|---|---|
| HDMP-1536A | Fibre Channel Transceiver Chip(光纖通道收發(fā)器芯片) |
| HDMP-1636 | Software |
| HDMP-1646 | Gigabit Ethernet Transceiver Chip |
| HDMP-1646A | Gigabit Ethernet Serialize/Deserialize (SerDes) IC(千兆位以太網(wǎng)串行器/解串行器) |
| HDMP-1636A | Gigabit Ethernet Serialize/Deserialize (SerDes) IC(千兆位以太網(wǎng)串行器/解串行器) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HDMP-1636 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Gigabit Ethernet Transceiver Chip |
| HDMP-1636A | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Gigabit Ethernet and Fibre Channel SerDes ICs |
| HDMP-1636AG | 制造商:PMC-Sierra 功能描述:1.06/1.25 GB SerDes for GB EOL301107 |
| HDMP-1637A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1.25 GBd SerDes Circuit with Differential PECL Clock Inputs for Gigabit Ethernet Applications |
| HDMP-1638 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Gigabit Ethernet Transceiver Chip with Dual Serial I/O and Differential PECL Clock Inputs |
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