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HDMP-T1636A Transceiver
HDMP-1636A Transceiver
HDMP-1646A Transceiver
Features
IEEE 802.3z Gbit Ethernet
Compatible, Supports 1250
MBd Gigabit Ethernet
Based on X3T11 “10 Bit
Specification”
Better Setup Time than
802.3z
Low Power Consumption
Transmitter and Receiver
Functions Incorporated onto
a Single IC
Three Package Sizes
Available:
– 10 mm TQFP (HDMP-T1636A)
– 10 mm PQFP (HDMP-1636A)
– 14 mm PQFP (HDMP-1646A)
10-Bit Wide Parallel TTL
Compatible I/Os
Single +3.3 V Power Supply
5-Volt Tolerant I/Os
2 kV ESD (Human Body
Model) Protection
Applications
1250 MBd Gigabit Ethernet
Interface
High Speed Proprietary
Interface
Backplane Serialization
Bus Extender
Description
The HDMP-1636A/46A/T1636A
transceiver is a single silicon
bipolar integrated circuit packaged
Gigabit Ethernet SerDes IC
Technical Data
in a plastic QFP package. It
provides a low-cost, low-power
physical layer solution for 1250
MBd Gigabit Ethernet or
proprietary link interfaces. It
provides complete Serialize/
Deserialize (SerDes) for copper
transmission, incorporating both
the Gigabit Ethernet transmit and
receive functions into a single
device.
This chip is used to build a high
speed interface (as shown in
Figure 1) while minimizing board
space, power and cost. It is
compatible with the IEEE 802.3z
specification.
The transmitter section accepts
10-bit wide parallel TTL data and
serializes this data into a high
speed serial data stream. The
parallel data is expected to be
“8B/10B” encoded data, or equiv-
alent. This parallel data is latched
into the input register of the
transmitter section on the rising
edge of the 125 MHz reference
clock (used as the transmit byte
clock).
The transmitter section’s PLL
locks to the user supplied 125
MHz byte clock. This clock is
then multiplied by 10 to generate
the 1250 MHz serial clock used
to generate the high speed
output. The high speed outputs
are capable of interfacing directly
to copper cables for electrical
transmission or to a separate
fiber optic module for optical
transmission.
The receiver section accepts a
serial electrical data stream at
1250 MBd and recovers the
original 10-bit wide parallel data.
The receiver PLL locks onto the
incoming serial signal and
recovers the high speed serial
clock and data. The serial data is
converted back into 10-bit
parallel data, recognizing the
8B/10B comma character to
establish byte alignment.
The recovered parallel data is
presented to the user at TTL
compatible outputs. The receiver
section also recovers two 62.5
MHz receiver byte clocks which
are 180 degrees out of phase
with each other. The parallel data
is properly aligned with the rising
edge of alternating clocks.
CAUTION: As with all semiconductor ICs, it is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by electrostatic discharge (ESD).