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參數(shù)資料
| 型號： | HDMP-1546A |
| 英文描述： | Fibre Channel Transceiver Chip(光纖通道收發(fā)器芯片) |
| 中文描述： | 光纖通道收發(fā)器芯片（光纖通道收發(fā)器芯片） |
| 文件頁數(shù)： | 8/16頁 |
| 文件大?。?/td> | 246K |
| 代理商： | HDMP-1546A |
8
AC Electrical Specifications
T
A[1]
= 0
°
C to +70
°
C, V
CC
= 3.15 V to 3.45 V
Symbol
t
r,REFCLK
REFCLK Rise Time, 0.8 to 2.0 volts
t
f,REFCLK
REFCLK Fall Time, 2.0 to 0.8 volts
t
r,TTLin
Input TTL Rise Time, 0.8 to 2.0 Volts
t
f,TTLin
Input TTL Fall Time, 2.0 to 0.8 Volts
t
r,TTLout
Output TTL Rise Time, 0.8 to 2.0 Volts, 10 pF Load
t
f,TTLout
Output TTL Fall Time, 2.0 to 0.8 Volts, 10 pF Load
t
rs,HS_OUT
HS_OUT Single-Ended (+DOUT) Rise Time
t
fs,HS_OUT
HS_OUT Single-Ended (+DOUT) Fall Time
t
rd,HS_OUT
HS_OUT Differential Rise Time
t
fd,HS_OUT
HS_OUT Differential Fall Time
V
IP,HS_IN
HS_IN Input Peak-to-Peak Differential Voltage
V
OP,HS_OUT[2]
HS_OUT Output Peak-to-Peak Differential Voltage
Parameter
Units
nsec
nsec
nsec
nsec
nsec
nsec
psec
psec
psec
psec
mV
mV
Min.
0.7
0.7
Typ.
Max.
2.4
2.4
2
2
1.5
1.1
225
200
225
200
1200
1600
2.4
2.4
375
375
200
1200
2000
2200
Notes:
1. Device tested and characterized under T
A
conditions specified, with T
C
monitored at approximately 20
°
higher than T
A
.
2. Output Peak-to-Peak Differential Voltage specified as DOUT+ minus DOUT-.
a. Differential HS_OUT Output (Dout+ Minus Dout-).
Figure 7. Transmitter DOUT Eye Diagrams.
b. Single-Ended HS_OUT Output (Dout+).
Eye Diagrams of the High-Speed Serial Outputs from the HDMP-1536/46A
as Captured on the HP 83480A Digital Communications Analyzer. Tested with PRBS = 2
7
-1.
Yaxis = 400 mV/DIV
22.0680 ns
200.0 ps/div
22.0680 ns
200.0 ps/div
Yaxis = 200 mV/DIV
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| HDMP-1636 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Gigabit Ethernet Transceiver Chip |
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| HDMP-1637A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1.25 GBd SerDes Circuit with Differential PECL Clock Inputs for Gigabit Ethernet Applications |
| HDMP-1638 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Gigabit Ethernet Transceiver Chip with Dual Serial I/O and Differential PECL Clock Inputs |
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