參數(shù)資料
型號(hào)： HDMP-1024
英文描述： Low Cost Gigabit Rate Receive Chip Set with TTL I/Os(帶TTL輸入/輸出的低價(jià)格千兆位速率接收芯片)
中文描述： 低成本千兆速率接收芯片組配備TTL的I / O（帶的TTL輸入/輸出的低價(jià)格千兆位速率接收芯片）
文件頁(yè)數(shù)： 8/40頁(yè)
文件大?。?/td> 363K
代理商： HDMP-1024
8
E
L
T
FLAG
DAV*
CAV*
FF
ERROR
CLOCK
SELECT
VCO
FILTER
PHASE /
FREQ
DETECT
INPUT
SELECT
CAP0
CAP1
0.1 μF
INPUT
SAMPLER
FRAME
DEMUX
CLOCK
GENERATOR
STATE
MACHINE
D-FIELD
DECODER
C-FIELD
DECODER
LINKRDY
*
STAT1
STAT0
D0..D19
DIN
±
LIN
±
T
D
D
S
S
A
FLAGSEL
M
S
INTERNAL
CLOCKS
FDIS
HDMP-1024 Rx Block
Diagram
The HDMP-1024 receiver was
designed to convert a serial data
signal sent from the HDMP-1022
into either 16,17, 20, or 21 bit
wide parallel data. In doing this, it
performs the functions of
Clock Recovery
Data Recovery
Demultiplexing
Frame Decoding
Frame Synchronization
Frame Error Detection
Link State Control
Input Select
The input select block determines
which input line is used. In
normal operation (LOOPEN=0),
DIN is accepted as the input
signal. For improved distance and
BER using coax cable, an input
equalizer may be used by
asserting EQEN. By setting
LOOPEN high, the receiver
accepts LIN as the input signal.
This feature allows for loop back
testing exclusive of the
transmission medium.
Phase/Frequency Detect
This block compares either the
phase or the frequency of the
incoming signal to the internal
serial clock generated from the
Clock Select block. The frequency
detect disable pin (FDIS) is set
high to disable the frequency
detector and enable the phase
detector. See
HDMP-1024 (Rx)
Phase Locked Loop
for more
details. The output of this block,
PH1, is used by the filter to
determine the control signal for
the VCO.
Filter
This is a loop filter that accepts
the PH1 output from the Phase/
Frequency Detector and converts
it into a control signal for the
VCO. This control signal tells the
VCO whether to increase or
decrease its frequency. The Filter
uses the PH1 input to determine a
proportional signal and an
integral signal. The proportional
signal determines whether the
VCO should increase or decrease
its frequency. The integral signal
filters out the high frequency PH1
signal and stores a historical PH1
output level. The two signals
combined determine the magni-
tude of frequency change of the
VCO.
VCO
This is the Voltage Controlled
Oscillator that is controlled by the
output of the Filter. It outputs a
high speed digital signal to the
Clock Select.
Figure 5. HDMP-1024 Receiver Block Diagram.
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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