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參數(shù)資料
| 型號(hào)： | HDMP-1024 |
| 英文描述： | Low Cost Gigabit Rate Receive Chip Set with TTL I/Os(帶TTL輸入/輸出的低價(jià)格千兆位速率接收芯片) |
| 中文描述： | 低成本千兆速率接收芯片組配備TTL的I / O（帶的TTL輸入/輸出的低價(jià)格千兆位速率接收芯片） |
| 文件頁數(shù)： | 1/40頁 |
| 文件大?。?/td> | 363K |
| 代理商： | HDMP-1024 |
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Low Cost Gigabit Rate
Transmit/Receive Chip Set with
TTL I/Os
Technical Data
Features
Virtual Ribbon Cable
Replacement
On-Chip Encode / Decode
On-Chip State Machine for
Fully Automatic Link
Management
On-Chip Tx/Rx PLL Provides
Frame Synchronization
High Speed Serial Rate
150-1500 MBaud
(User Selectable)
Standard TTL Interface
16, 17, 20, or 21 Bits Wide
Implemented in a Low Cost
Aluminum M-Quad 80
Package
Applications
Backplane Serialization/
Bus Extender
Video, Image Acquisition
Point to Point Data Links
Implement SCI-FI Standard
Implement Serial HIPPI
Specification
From the user’s viewpoint, these
products can be thought of as
providing a “virtual ribbon cable”
interface for the transmission of
data. Parallel data (a frame)
loaded into the Tx (transmitter)
chip is delivered to the Rx
(receiver) chip over a serial
channel, which can be either a
coaxial copper cable or optical
link, and is reconstructed into its
original parallel form.
The chip set hides from the user
all the complexity of encoding,
multiplexing, clock extraction,
demultiplexing and decoding.
Unlike other links, the phase-
locked-loop clock extraction
circuit also transparently provides
for frame synchronization–the
user is not troubled with the
periodic insertion of frame syn-
chronization words. In addition,
the DC balance of the line code is
automatically maintained by the
chip set. Thus, the user can
transmit arbitrary data without
restriction. The Rx chip also
includes a state-machine con-
troller (SMC) that provides a
startup handshake protocol for
the duplex link configuration.
The serial data rate of the Tx/Rx
link is selectable in four ranges
(see tables on page 5), and
extends from 120 Mbits/s up to
1.25 Gbits/s. This translates into
an encoded serial rate of 150-1500
MBaud. The parallel data interface
is 16 or 20 bit TTL, pin selectable. A
flag bit is available and can be used
as an extra 17th or 21st bit under
the user’s control. The flag bit can
also be used as an even or odd
frame indicator for dual-frame
transmission. If not used, the link
performs expanded error detection.
The serial link is synchronous, and
both frame synchronization and bit
synchronization are maintained.
When data is not available to send,
the link maintains synchronization
by transmitting fill frames. Two
(training) fill frames are reserved
for handshaking during link startup.
User control space is also sup-
ported. If Control Available (CAV) is
asserted at the Tx chip, the least
significant 14 or 18 bits of the data
are sent and the Rx Control
Available (CAV) line will indicate
the data as a Control Word.
HDMP-1022 Transmitter
HDMP-1024 Receiver
Description
The HDMP-1022 transmitter and
the HDMP-1024 receiver are used
to build a high-speed data link for
point-to-point communication.
The monolithic silicon bipolar
transmitter chip and receiver chip
are each provided in a standard
aluminum M-Quad 80 package.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HDMP-1032 | 1.4 GBd Transmitter Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 傳送器) |
| HDMP-1034 | 1.4 GBd Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 接收器) |
| HDMP-1512 | Fibre Channel Transmitter Chipset(光纖通道傳送芯片) |
| HDMP-1514 | Fibre Channel Receiver Chipset(光纖通道接收芯片) |
| HDMP-1526 | Transistor Diode Kit;Contents Of Kit:Transistor/Diode Kit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HDMP-1032 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1032A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1.4 GBd Transmitter Chip with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1034 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1034A | 制造商:HP 制造商全稱:Agilent(Hewlett-Packard) 功能描述:Transmitter/Receiver Chip Set |
| HDMP-1512 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transmitter and Receiver Chipset |
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