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參數(shù)資料
| 型號(hào)： | HDMP-1024 |
| 英文描述： | Low Cost Gigabit Rate Receive Chip Set with TTL I/Os(帶TTL輸入/輸出的低價(jià)格千兆位速率接收芯片) |
| 中文描述： | 低成本千兆速率接收芯片組配備TTL的I / O（帶的TTL輸入/輸出的低價(jià)格千兆位速率接收芯片） |
| 文件頁(yè)數(shù)： | 19/40頁(yè) |
| 文件大?。?/td> | 363K |
| 代理商： | HDMP-1024 |
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19
Rx I/O Definition
Name
ACTIVE
Pin
25
Type
I-TTL
Signal
Chip Enable:
This input is normally driven by the Rx state machine
output. The ACTIVE signal is internally retimed by STRBOUT and
presented to the user as the LINKRDY* signal. This is how the Rx
state machine signals the user that the start-up sequence is complete.
Loop Filter Capacitor:
A loop filter capacitor of 0.1
μ
F must be
connected across the CAP0B and CAP1B inputs to increase the loop time
constant.
Control Frame Available Output:
This active-low output indicates
that the Rx chip data outputs are receiving Control Frames. False
CAV* indications may be generated during link startup.
Data Outputs:
20 Bit data is received and decoded when M20SEL is
active; otherwise 16 bit data is decoded and the D16-D19 bits
are undefined.
CAP0B
CAP1B
1
4
C
CAV*
38
O-TTL
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
DAV*
71
70
69
68
67
66
65
60
59
58
57
56
55
54
51
50
49
48
47
46
37
O-TTL
O-TTL
Data Available Output:
This active-low output indicates that the
Rx chip data outputs, D0..D19, have received data frames. Data
should be latched on the rising edge of STRBOUT. Note that during
link startup, false data indications may be given. The DAV* and
LINKRDY* outputs can be used together to avoid confusion during
link startup.
Normal Serial Data Input:
This is the input used when LOOPEN
is not active. When LOOPEN is high, the loop back data inputs LIN,
LIN* are used instead. An optional cable equalizer may be enabled for
the DIN, DIN* inputs by asserting EQEN.
VCO Divider Select:
These two pins program the VCO divider chain
to operate at full speed, half speed, quarter speed or one-eighth speed.
Enable Input for Cable Equalization:
When asserted, this signal
activates the cable equalization amplifier on the DIN, DIN* serial
data inputs.
DIN
DIN*
15
14
I-H50
DIV0
DIV1
EQEN
6
7
19
I-TTL
I-TTL
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| HDMP-1032 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate |
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| HDMP-1034 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1034A | 制造商:HP 制造商全稱:Agilent(Hewlett-Packard) 功能描述:Transmitter/Receiver Chip Set |
| HDMP-1512 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Fibre Channel Transmitter and Receiver Chipset |
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