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參數(shù)資料
| 型號(hào)： | HDMP-1024 |
| 英文描述： | Low Cost Gigabit Rate Receive Chip Set with TTL I/Os(帶TTL輸入/輸出的低價(jià)格千兆位速率接收芯片) |
| 中文描述： | 低成本千兆速率接收芯片組配備TTL的I / O（帶的TTL輸入/輸出的低價(jià)格千兆位速率接收芯片） |
| 文件頁(yè)數(shù)： | 39/40頁(yè) |
| 文件大小： | 363K |
| 代理商： | HDMP-1024 |
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39
Figure 22. I-H50 and O-BLL Simplified Circuit Schematic.
Mode Options
G-Link has several option pins
which set the modes of operation.
Common to both the Tx and the
Rx are M20SEL, DIV0, and DIV1,
FLAGSEL, and LOOPEN. Local to
the Tx are MDFSEL, EHCLKSEL,
and HCLKON. Local to the Rx are
EQEN and TCLKSEL. These pins
are all I-TTL, and can be set as
described below.
M20SEL sets the width of the
frame to 16/20 bits.
DIV1 / DIV0 sets the frequency
bands of operation. Refer to the
Setting the Operating Data Rate
Range
section for frequency band
selection. It is recommended that
applications near the ends of the
bands have jumpers for DIV0 and
DIV1 inputs, so that the board can
accommodate possible lot-to-lot
band variations over the life of the
board design.
FLAGSEL selects whether the flag
bit is reserved for error detection
by the link, or used as an extra bit
available for the user.
LOOPEN selects whether the
normal data (DIN/ DIN*) or the
loop back data (LIN/ LIN*) are
used.
MDFSEL selects the Tx single or
double frame modes.
ECHKSEL selects whether to lock
onto a frame-rate clock at
STRBIN or to use this clock as the
high speed clock and bypass the
PLL in the Tx. This input is used
mainly for testing, and should be
normally set low.
HCLKON turns on the high speed
serial clock outputs of the Tx.
This option was added to
conserve power.
EQEN disables or enables the
data equalizer in the Rx for cable
applications.
TCLKSEL selects the clock source
from either the serial data stream
or from the TCLK inputs for the
Rx. This input is for testing only,
and should normally be set low.
Z
o
= 50
V
EE
28 mA
80
80
50
50
50
V
CC
O-BLL
I-H50
0.1 μF
50
V
CC_HS
0.1 μF
0.1 μF
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