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參數(shù)資料
| 型號： | HDMP-1014 |
| 英文描述： | Bipolar Transistor; Collector Emitter Voltage, Vceo:400V; Transistor Polarity:N Channel; Power Dissipation:250W; C-E Breakdown Voltage:400V; DC Current Gain Min (hfe):10; Collector Current:50A; Package/Case:TO-3 |
| 中文描述： | 4Low成本千兆速率發(fā)送/接收芯片組 |
| 文件頁數(shù)： | 21/42頁 |
| 文件大?。?/td> | 321K |
| 代理商： | HDMP-1014 |
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593
Rx I/O Definition (cont’d.)
Name
LIN LIN*
Pin
18
17
Type
I-H50
Signal
Loop Back Serial Data Input:
Use this input when LOOPEN is
active. Unlike the DIN, DIN* inputs, this input does not have a cable
equalizer. In normal usage, this input will be connected to the Tx
chip LOUT, LOUT* outputs. This allows the user to check the
near-end functionality of the Tx and Rx pair independent of the
transmission medium
Loop Back Control:
When asserted, this signal causes the loop back
data inputs LIN, LIN* to be used instead of the normal data inputs
DIN, DIN*.
Link Ready Indicator:
This active-low output is a retimed version
of the ACTIVE input. ACTIVE is normally driven by the Rx state
machine output. LINKRDY* then indicates that the startup sequence
is complete and that the data and control indications are valid.
16 or 20 Bit Word Select:
When this signal is high, the link operates
in 20 Bit data reception mode. Otherwise, the link operates in 16 Bit
mode and data outputs D16-D19 are undefined.
Nibble Clock Monitor:
Leave unterminated in normal use.
Temperature Sense Diode:
Used during wafer and package test
only. It should be left open.
Phase Detector Test Output:
The output from the phase/frequency
detector in the Rx PLL. When PH1 is high, the VCO should increase
frequency. When low, the VCO should decrease frequency.
State Machine Reset Inputs:
Each of these active-low input pins
reset the Rx state machine to the initial start-up state. This initiates
a complete PLL restart and handshake at both ends of the duplex
link. Normally, SMCRST0* is connected to a power-up reset circuit
or a host system reset signal. The SMCRST1* input is normally
connected to the Tx LOCKED output. The LOCKED signal holds the
state-machine in the start-up state until the Tx PLL is locked.
State Machine Status Outputs:
These outputs indicate the current
state-machine state. They are used to directly control the Tx ED,
Tx FF, Rx FDIS, and Rx ACTIVE lines.
Recovered Frame-rate Data Clock Output:
This output is the PLL
recovered frame rate clock. D0-D19, FLAG, DAV, CAV, FF, LINKRDY,
and ERROR should all be latched on the rising edge of STRBOUT.
External VCO Replacement Test Clock:
When TCLKSEL in
enabled, this input is used in place of the normal VCO signal,
effectively disabling the PLL and allowing the user to provide an
external retiming clock for testing.
Enable Test Clock Input:
When this input is active, the TCLK,
TCLK* inputs are used in place of the normal VCO signal. This
feature is useful both for synchronous systems and for chip testing.
LOOPEN
16
I-ECL
LINKRDY*
36
O-ECL
M20SEL
30
I-ECL
NCLK
TEMP
76
77
O-ECL
T
PH1
79
O-ECL
SMRST0*
SMRST1*
28
29
I-ECL
STAT0
STAT1
27
26
O-ECL
STRBOUT
35
O-ECL
TCLK
TCLK*
12
11
I-H50
TCLKSEL
10
I-ECL
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