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參數(shù)資料
| 型號： | HDMP-1014 |
| 英文描述： | Bipolar Transistor; Collector Emitter Voltage, Vceo:400V; Transistor Polarity:N Channel; Power Dissipation:250W; C-E Breakdown Voltage:400V; DC Current Gain Min (hfe):10; Collector Current:50A; Package/Case:TO-3 |
| 中文描述： | 4Low成本千兆速率發(fā)送/接收芯片組 |
| 文件頁數(shù)： | 10/42頁 |
| 文件大小： | 321K |
| 代理商： | HDMP-1014 |
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582
HDMP-1012 (Tx) Timing
Figure 6 shows the Tx timing
diagram. Under normal
operations, the Tx PLL locks an
internally generated clock to the
incoming STRBIN. The incoming
data, D0-D19, ED, FF, DAV*,
CAV*, and FLAG, are latched by
this internal clock. For
MDFSEL=0, the input rate of
STRBIN is expected to be the
same as the parallel data rate. For
MDFSEL=1, STRBIN should be 1/
2 of the incoming parallel data
rate. The data must be valid
before it’s sampled for the set-up
time (t
s
), and remain valid after
it’s sampled for the hold time (t
h
).
The set-up and hold times are
referenced to STRBIN. This
reference is the positive edge of
STRBIN for MDFSEL=0, and is 1/
2 the frame period from the
positive or negative edge of
STRBIN for MDFSEL=1.
STRBOUT appears after this
reference with a delay of T
strb
.
The rate of STRBOUT is always
the same as the word rate of the
incoming data, independent of
MDFSEL.
The start of a frame, D0, in the
high speed serial output occurs
after a delay of td after the rising
edge of the STRBIN. The typical
value of td may be calculated by
using the following formula:
td = ( 2 * serial bit duration -
0.5 ns) ns
Figure 6. HDMP-1012 (Tx) Timing Diagram.
HDMP-1012 (Tx) Timing Characteristics
Tc = 0
°
C to +85
°
C, V
EE
= -4.5 V to -5.5 V
Symbol
t
s
Setup Time, for Rising Edge of STRBIN Relative to
D0-D19, ED, FF, DAV*, CAV* and FLAG
t
h
Hold Time, for Rising Edge of STRBIN Relative to
D0-D19, ED, FF, DAV*, CAV* and FLAG
T
strb
STRBOUT - STRBIN Delay
Parameter
Units
nsec
Min.
6
Typ.
Max.
nsec
0
nsec
1.5
3
1/2 FRAME PERIOD
t
s
t
h
t
strb
t
d
D-FIELD
C-FIELD
STRBIN
MDFSEL = 0
STRBIN
MDFSEL = 1
D00 - D19
ED, FF
DAV*, CAV*
FLAG
STRBOUT
DOUT
HCLK
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