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參數資料
| 型號： | HDMP-0552 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | AGILENT HDMP-0552 QUAD PORT BYPASS CIRCUIT WITH CDR AND DATA VALID DETECTION |
| 中文描述： | 安捷倫劑量甲基強的松龍與CDR和數據有效0552四端口旁路電路檢測 |
| 文件頁數： | 3/12頁 |
| 文件大?。?/td> | 266K |
| 代理商： | HDMP-0552 |
3
Equalizer Input
All FM_NODE[n]+ high-speed
differential inputs have an
equalization setting to offset the
effects of skin loss and dispersion
on PCBs. This function is
independently controllable for
each input port using the EQ_SEL
and NDx (x = 0-4) pins. The
default setting for the equalization
is TRUE. Equalization maybe set
to FAULT for individual inputs
by forcing EQ_SEL low and NDx
(where x = port number) low for
each port that the equalization
setting is desired to be false. It is
a logic OR function. For instance,
forcing EQ_SEL, ND2 & ND3 pins
low will turn off the equalization
setting at FM_NODE[2]+ and
FM_NODE[3]+ while the
equalization setting will remain
on for ports 0, 1 and 4.
The EQ_SEL and NDx (x = 0-4)
pins are LVTTL and contain
internal pull-up circuitry. To
force a pin low each pin should
be connected to GND through a
1 k
W
resistor. Otherwise, these
inputs should be left to float. In
this case, the internal pull-up
circuitry will force them high.
BYPASS[n]- Input
The active low BYPASS[n]- inputs
control the data flow through the
HDMP-0552. All BYPASS pins
are LVTTL and contain internal
pull-up circuitry. To bypass a
port, the appropriate BYPASS[n]-
pin should be connected to GND
through a 1 k
W
resistor.
Otherwise, the BYPASS[n]-
inputs should be left to float. In
this case, the internal pull-up
circuitry will force them high.
Figure 1 - Block Diagram of HDMP-0552
BLL Output
All TO_NODE[n]+ high-speed
differential outputs are driven by
a Buffered Line Logic (BLL)
circuit that has on-chip source
termination. Therefore, no
external bias resistors are
required. The BLL outputs on the
HDMP-0552 are of equal strength.
Unused outputs should be
turned off independently. This
reduces power and reduces the
potential for crosstalk effects
caused by incorrect
terminations.
If the unused
outputs are not turned off they
should be differentially
terminated. The value of the
termination resistor should
match the PCB trace differential
impedance. Each output port is
set to active or inactive by the
OUT_SEL and NDx (x = 0-4) pins.
T
F
B
T
F
B
T
F
B
T
F
B
T
F
B
1
0
B
1
0
B
1
0
B
1
0
B
1
0
0
1
0
1
CDR
CPLL
M
T
C
T
F
T
DV
T
F
S
C
T
R
T
R
AV
T
F
T
B
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